Appendix E: Jetson Tx2/Tx2I Pin Descriptions - Nvidia Jetson TX2 Manual

20.0 APPENDIX E: JETSON TX2/TX2I PIN DESCRIPTIONS

Table 93. Jetson TX2/TX2i Connector (8x50) Pin Descriptions
Pin # Module Pin Name
A1 VDD_IN
A2 VDD_IN
A3 GND
A4 GND
A5 RSVD
A6 I2C_PM_CLK
A7 CHARGING#
A8 GPIO14_AP_WAKE_MDM
A9 GPIO15_AP2MDM_READY
A10 GPIO16_MDM_WAKE_AP
A11 JTAG_GP1
A12 JTAG_TMS
A13 JTAG_TDO
A14 JTAG_RTCK
A15 UART2_CTS#
A16 UART2_RTS#
A17 USB0_EN_OC#
A18 USB1_EN_OC#
A19 RSVD
A20 I2C_GP1_DAT
A21 I2C_GP1_CLK
A22 GPIO_EXP1_INT
A23 GPIO_EXP0_INT
A24 LCD1_BKLT_PWM
A25 LCD_TE
A26 GSYNC_HSYNC
A27 GSYNC_VSYNC
A28 GND
A29 SDIO_RST#
SDIO_D3
A30
SDIO_D2
A31
SDIO_D1
A32
A33 DP1_HPD
A34 DP1_AUX_CH–
A35 DP1_AUX_CH+
A36 USB0_OTG_ID
A37 GND
A38 USB1_D+
A39 USB1_D–
A40 GND
A41 PEX2_REFCLK+
A42 PEX2_REFCLK–
A43 GND
A44 PEX0_REFCLK+
A45 PEX0_REFCLK–
A46 RESET_OUT#
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Tegra Signal Usage/Description
Main power – Supplies PMIC & external
−
supplies
− GND
− GND
− Not used
GEN8_I2C_SCL PM I2C Clock
(PMIC GPIO5) Charger Interrupt
UFS0_RST AP (Tegra) Wake Modem or GPIO
UFS0_REF_CLK AP (Tegra) to Modem Ready or GPIO
GPIO_MDM2 Modem Wake AP (Tegra) or GPIO
JTAG General Purpose 1. Pulled low on
module for normal operation & pulled
NVJTAG_SEL
high by test device for Boundary Scan
test mode.
JTAG_TMS JTAG Test Mode Select
JTAG_TD0 JTAG Test Data Out
− JTAG Return Clock
UART2_CTS UART 2 Clear to Send
UART2_RTS UART 2 Request to Send
USB_VBUS_EN0 USB VBUS Enable/Overcurrent 0
USB_VBUS_EN1 USB VBUS Enable/Overcurrent 1
− Not used
GEN1_I2C_SDA General I2C 1 Data
GEN1_I2C_SCL General I2C 1 Clock
GPIO_MDM7 GPIO Expander 1 Interrupt or GPIO
GPIO_MDM1 GPIO expander 0 Interrupt or GPIO
GPIO_DIS5 Display Backlight PWM 1
GPIO_DIS1 Display Tearing Effect
GPIO_DIS4 GSYNC Horizontal Sync
GPIO_DIS2 GSYNC Vertical Sync
− GND
GPIO_WAN3 Secondary WLAN Enable
SDMMC3_DAT3 SDIO Data 3
SDMMC3_DAT2 SDIO Data 2
SDMMC3_DAT1 SDIO Data 1
DP_AUX_CH1_HPD Display Port 1 Hot Plug Detect
DP_AUX_CH1_N Display Port 1 Aux– or HDMI DDC SDA
DP_AUX_CH1_P Display Port 1 Aux+ or HDMI DDC SCL
(PMIC GPIO0) USB 0 ID / VBUS EN
− GND
USB1_DP USB 2.0, Port 1 Data+
USB1_DN USB 2.0, Port 1 Data–
− GND
PEX_CLK2P PCIe 2 Reference Clock+ (PCIe IF #1)
PEX_CLK2N PCIe 2 Reference Clock– (PCIe IF #1)
− GND
PEX_CLK1P PCIe 0 Reference Clock+ (PCIe IF #0)
PEX_CLK1N PCIe 0 Reference Clock – (PCIe IF #0)
Reset Out. Reset from PMIC (through
diodes) to Tegra & eMMC reset pins.
Driven from carrier board to force reset
of Tegra & eMMC (not PMIC). An
SYS_RESET_N
xternal 100kΩ pull-up to 1.8V near
e
Tegra (module pin side) & external
10kΩ pull-up to 1.8V on the other
side of a diode
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Usage on the Carrier
Board
Main DC input
GND
GND
I2C (General)
System
M.2 Key E
JTAG
JTAG Header & Debug
Connector
M.2 Key E
USB 2.0 Micro AB
USB 3.0 Type A
I2C (General)
GPIO Expander
Display Connector
GND
M.2 Key E
SDIO
HDMI Type A Conn.
USB 2.0 Micro AB
GND
USB 3.0 Type A
GND
Unassigned
GND
PCIe x4 Connector
System
(PMIC side).
Direction Pin Type
5.5V-19.6V (TX2)
Input
9.0V-19.0V (TX2i)
−
−
− −
Bidir Open Drain – 1.8V
Input CMOS – 1.8V
Output CMOS – 1.8V
Output CMOS – 1.8V
Input CMOS – 1.8V
Input CMOS – 1.8V
Input CMOS – 1.8V
Output CMOS – 1.8V
Input CMOS – 1.8V
Input CMOS – 1.8V
Output CMOS – 1.8V
Bidir Open Drain – 3.3V
Bidir Open Drain – 3.3V
− −
Bidir Open Drain – 3.3V
Bidir Open Drain – 3.3V
Input CMOS – 1.8V
Input CMOS – 1.8V
Output CMOS – 1.8V
Input CMOS – 1.8V
Output CMOS – 1.8V
Output CMOS – 1.8V
−
Output CMOS – 1.8V
Bidir CMOS – 1.8V
Bidir CMOS – 1.8V
Bidir CMOS – 1.8V
Input CMOS – 1.8V
Bidir AC-Coupled on Carrier
Board (eDP/DP) or Open-
Drain, 1.8V (3.3V tolerant -
Bidir
DDC/I2C)
Input
−
Bidir
USB PHY
Bidir
−
Output
PCIe PHY
Output
−
Output
PCIe PHY
Output
Bidir CMOS – 1.8V
GND
GND
−
−
GND
Analog
GND
GND
GND
95