Uart - Nvidia Jetson TX2 Manual

Table 72. SPI Interface Signal Routing Requirements
Parameter
Max Frequency
Configuration / Device Organization
Max Loading (total of all loads)
Reference plane
Breakout Region Impedance
Max PCB breakout delay
Trace Impedance
Via proximity (Signal to reference)
Trace spacing
Max Trace Length/De lay (PCB Main Trunk)
For MOSI, MISO, SCK & CS
Max Trace Length/De lay (Branch-A)
for MOSI, MISO, SCK & CS
Max Trace Length/De lay (Branch-B)
for MOSI, MISO, SCK & CS
Max Trace Length/Delay Skew from MOSI, MISO & CS to SCK
Note: Up to 4 signal Vias can share a single GND return Via
Table 73. SPI Signal Connections
Module Pin Names Type
SPI[2:0]_CLK I/O
SPI[2:0]_MOSI I/O
SPI[2:0]_MISO I/O
SPI2_CS[1:0]# I/O
SPI[1:0]_CS0#
Table 74. Recommended SPI observation (test) points for initial boards
Test Points Recommended
One for each SPI signal line used

12.3 UART

Jetson TX2/TX2i brings five UARTs out to the main connector. One of the UARTs is used for the WLAN/BT on Jetson TX2 or
as UART3 at the connector depending on the setting of a multiplexor. See Table 76 for typical assignments of the UARTs.
Table 75. UART Pin Descriptions
Pin # Module Pin Name
H11 UART0_CTS#
G11 UART0_RTS#
G12 UART0_RX
H12 UART0_TX
E10 UART1_CTS#
E9 UART1_RTS#
D10 UART1_RX
D9 UART1_TX
A15 UART2_CTS#
A16 UART2_RTS#
B15 UART2_RX
B16 UART2_TX
G9 UART3_CTS#
G10 UART3_RTS#
H9 UART3_RX
H10 UART3_TX
D5 UART7_RX
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Microstrip / Stripline
Point-Point
2x-Load Star/Daisy
2x-Load Star/Daisy
2x-Load Star/Daisy
Termination
SPI0_CLK has 120Ω Bead in series
(on the module).
Location
Near the module & Device pins.
Tegra Signal Usage/Description
UART1_CTS UART 0 Clear to Send
UART1_RTS UART 0 Request to Send
UART1_RX UART 0 Receive
UART1_TX UART 0 Transmit
UART3_CTS UART 1 Clear to Send
UART3_RTS UART 1 Request to Send
UART3_RX UART 1 Receive
UART3_TX UART 1 Transmit
UART2_CTS UART 2 Clear to Send
UART2_RTS UART 2 Request to Send
UART2_RX UART 2 Receive
UART2_TX UART 2 Transmit
UART4_CTS_N UART 3 Clear to Send (muxed on TX2)
UART4_RTS_N UART 3 Request to Send (muxed on TX2)
UART4_RX UART 3 Receive (muxed on TX2)
UART4_TX UART 3 Transmit (muxed on TX2)
UART7_RX UART 7 Receive
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Requirement
65
3
15
GND
Minimum width & spacing
75
50 – 60
< 3.8 (24)
4x / 3x
195 (1228)
120 (756)
75 (472)
75 (472)
16 (100)
Description
SPI Clock.: Connect to Peripheral CLK pin(s)
SPI Data Output: Connect to Slave Peripheral MOSI pin(s)
SPI Data Input: Connect to Slave Peripheral MISO pin(s)
SPI Chip Selects.: Connect one CS_N pin per SPI IF to each Slave
Peripheral CS pin on the interface
Usage on the Carrier
Board
Debug Header
Serial Port Header
M.2 Key E
Not assigned
Optional source of
UART on Exp. Header
Not Assigned
Units Notes
MHz
load
pF
ps
Ω ±15%
mm (ps) See Note 1
dielectric
mm (ps)
mm (ps)
mm (ps)
mm (ps) At any point
Direction Pin Type
Input CMOS – 1.8V
Output CMOS – 1.8V
Input CMOS – 1.8V
Output CMOS – 1.8V
Input CMOS – 1.8V
Output CMOS – 1.8V
Input CMOS – 1.8V
Output CMOS – 1.8V
Input CMOS – 1.8V
Output CMOS – 1.8V
Input CMOS – 1.8V
Output CMOS – 1.8V
Input CMOS – 1.8V
Output CMOS – 1.8V
Input CMOS – 1.8V
Output CMOS – 1.8V
Input CMOS – 1.8V
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