Nvidia Jetson TX2 Manual page 32

Table 24. PCIE Signal Connections
Module Pin Name
PCIe Interface #0 (x1 default configuration – x4 optional.
PEX0_TX+/– (Lane 0)
USB_SS1_TX+/– (Lane 1)
PEX2_TX+/– (Lane 2)
PEX_RFU_TX+/– (Lane 3)
PEX0_RX_+/– (Lane 0)
USB_SS1_RX+/– (Lane 1)
PEX2_RX+/– (Lane 2)
PEX_RFU_RX+/– (Lane 3)
PEX0_REFCLK+/–
PEX0_CLKREQ#
PEX0_RST#
PCIe Interface #1 (x1) – (Shared with PCIe Interface #0 lane 2)
PEX2_TX+/–
PEX2_RX+/–
PEX2_REFCLK+/–
PEX2_CLKREQ#
PEX2_RST#
PCIe Interface #2 (x1) – Muxed with USB 3.0 Port #0 on USB_SS0
PEX1_TX+/–
PEX1_RX+/–
PEX1_REFCLK+/–
PEX1_CLKREQ#
PEX1_RST#
PEX_WAKE#
Note: Check "Supported USB 3.0, PEX & SATA Interface Mappings" tables earlier in this section for PCIE IF mapping options.
Table 25. Recommended PCIe observation (test) points for initial boards
Test Points Recommended
One for each of the PCIe TX_+/– output lines used.
One for each of the PCIe RX_+/– input lines used.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Type Termination
DIFF OUT Series 0.1uF Capacitor
DIFF IN Series 0.1uF capacitors if
device on main PCB.
DIFF OUT
I/O 56KΩ pullup to
VDD_3V3_SYS on each line
O (exists on the module)
DIFF OUT Series 0.1uF Capacitor
DIFF IN Series 0.1uF capacitors if
device on main PCB.
DIFF OUT
I/O 56KΩ pullup to
VDD_3V3_SYS on each line
(exists on the module)
O
DIFF OUT Series 0.1uF Capacitor
DIFF IN Series 0.1uF capacitors if
device on main PCB.
DIFF OUT
I/O 56KΩ pullup to
VDD_3V3_SYS on each line
(exists on the module)
O
I 56KΩ pullup to
VDD_3V3_SYS (exists on the
module)
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Description
Differential Transmit Data Pairs: Connect to TX_P/N pins of PCIe
connector or RX_P/N pin of PCIe device through AC cap according to
supported configuration. Default configuration (x1) uses only Lane 0.
Differential Receive Data Pairs: Connect to RX_P/N pins of PCIe
connector or TX_P/N pin of PCIe device through AC cap according to
supported configuration. Default configuration (x1) uses only Lane 0.
Differential Reference Clock Output: Connect to REFCLK_P/N pins of
PCIe device/connector
PEX Clock Request for PEX0_REFCLK: Connect to CLKREQ pin on
device/connector.
PEX Reset: Connect to PERST pin on device/connector.
Differential Transmit Data Pairs: Connect to TX+/– pins of PCIe
connector or RX_+/– pin of PCIe device through AC cap according to
supported configuration.
Differential Receive Data Pairs: Connect to RX_+/– pins of PCIe
connector or TX_+/– pin of PCIe device through AC cap according to
supported configuration.
Differential Reference Clock Output: Connect to REFCLK_+/– pins of
PCIe device/connector.
PEX Clock Request for PEX2_REFCLK: Connect to CLKREQ pin on
device/connector(s)
PEX Reset: Connect to PERST pin on device/connector.
Differential Transmit Data Pairs: Connect to TX+/– pins of PCIe
connector or RX_+/– pin of PCIe device through AC cap according to
supported configuration.
Differential Receive Data Pairs: Connect to RX_+/– pins of PCIe
connector or TX_+/– pin of PCIe device through AC cap according to
supported configuration.
Differential Reference Clock Output: Connect to REFCLK_+/– pins of
PCIe device/connector
PEX Clock Request for PEX1_REFCLK: Connect to CLKREQ pin on
device/connector(s)
PEX Reset: Connect to PERST pin on device/connector(s)
PEX Wake: Connect to WAKE pins on devices or connectors
Location
Near PCIe device. Connector pins may serve as test points if accessible.
Near the module connector.
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