Nvidia Jetson TX2 Manual page 31

Termination
Impedance
Trace Impedance differential / Single Ended
Reference plane
Spacing
Trace Spacing (Stripline/Microstrip)
To plane & capacitor pad
To unrelated high-speed signals
Length/Skew
Trace loss characteristic @ 2.5GHz
Breakout region (Max Length)
Max trace length
Max PCB via distance from the BGA
PCB within pair (intra-pair) skew
Within pair (intra-pair) matching between
subsequent discontinuities
Differential pair uncoupled length
Via
Via placement
Max # of Vias
Max Via stub length
Routing signals over antipads
AC Cap
Value
Location (max length to adjacent discontinuity)
Voiding
Serpentine
Min bend angle
Dimension
MIsc.
Routing signals over antipads
Routing over voids
Connector
Voiding
Keep critical PCIe traces such as PEX_TX/RX, TERMP etc. away from other signal traces or unrelated power traces/areas or powe r supply components
Note: The PCIe spec. has 40-60Ω absolute min/max trace impedance, which can be used instead of the 50 Ω, ± 15%.
1.
If routing in the same layer is necessary, route group TX & RX separately without mixing RX/TX routes & keep distance
2.
between nearest TX/RX trace & RX to other signals 3x RX-RX separation.
Longer trace lengths may be possible if the total trace loss is equal to or better than the target. If the loss is greater, the
3.
max trace lengths will need to be reduced.
Do length matching before Via transitions to different layers or any discontinuity to minimize common mode conversion.
4.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
50
85 / 50
GND
Pair – Pair 3x / 4x
3x / 4x
3x / 4x
< 0.7
41.9
5.5 (880)
41.9
0.15 (0.5)
0.15 (0.5)
41.9
Place GND vias as symmetrically as possible to data pair vias. GND via distance should be placed
less than 1x the diff pair via pitch
PTH Vias 2 for TX traces & 2 for RX trace
Micro-Vias No requirement
0.4
Not allowed
Min/Max 0.075 / 0.2
8
Voiding the plane directly under the pad 3-4
mils larger than the pad size is
recommended.
135
Min A Spacing 4x
Min B, C Length 1.5x
Min Jog Width 3x
Not allowed
When signal pair approaches Vias, the maximal trace length across the void on the plane is 50mil.
Voiding the plane directly under the pad 5.7
mils larger than the pad size is
recommended.
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Ω To GND Single Ended for P & N
Ω ±15%. See note 1
Dielectric
dB/in The following max length is derived based on this
characteristic. See note 3
ps Minimum width and spacing. 4x or wider
dielectric height spacing is preferred
in (ps)
ps Max distance from BGA ball to first PCB via.
mm (ps) Do trace length matching before hitting
discontinuities
mm (ps)
ps
mm Longer via stubs would require review
uF Only required for TX pair when routed to connector
mm Discontinuity such as edge finger, component pad
deg (a)
S1 must be taken care in
order to consider Xtalk to
Trace width
adjacent pair
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