Nvidia Jetson TX2 Manual page 83

NVIDIA Jetson TX2/TX2i OEM Product Design Guide
DSI0_CK+/– connected to CLKp/n pins of the lower x4 DSI interface of display
DSI0_D[1:0] +/– connected to lower 2 data lanes of the lower x4 DSI interface of display
DSI1_D[1:0] +/– connected to upper 2 data lanes of the lower x4 DSI interface of display
DSI2_CK+/– connected to CLKp/n pins of the upper x4 DSI interface of display or a x4 DSI interface of secondary display
DSI2_D[1:0] +/– connected to lower 2 data lanes of the upper x4 DSI interface of display or lower 2 lanes of secondary display
DSI3_D[1:0] +/– connected to upper 2 data lanes of the upper x4 DSI interface of display or upper 2 lanes of secondary display
Any EMI/ESD devices used on DSI signals are suitable for highest frequencies supported (low capacitive load: <1pf recommended)
DSI Split Link Configurations
DSI0_CK+/– connected to CLKp/n pins of the 1st x2 DSI interface of split link display
DSI0_D[1:0] +/– connected to up to 2 data lanes of the 1st x1/x2 DSI interface of split link display
DSI1_CK+/– connected to CLKp/n pins of the 2nd x2 DSI interface of split link display
DSI1_D[1:0] +/– connected to up to 2 data lanes of the 2nd x1/x2 DSI interface of split link display
DSI2_CK+/– connected to CLKp/n pins of the 3rd x2 DSI interface of split link display
DSI2_D[1:0] +/– connected to up to 2 data lanes of the 3rd x1/x2 DSI interface of split link display
DSI3_CK+/– connected to CLKp/n pins of the 4th x2 DSI interface of split link display
DSI3_D[1:0] +/– connected to up to 2 data lanes of the 4th x1/x2 DSI interface of split link display
Any EMI/ESD devices used on DSI signals are suitable for highest frequencies supported (low capacitive load: <1pf recommended)
Display Control Connections
LCD_TE (used for Tearing Effect signal from display) connected to matching pin on display connector if supported
LCD_VDD_EN connected to enable of embedded display related power supply/load switch
LCD_BKLT_EN connected to enable of backlight solution(s)
LCD[1:0]_BKLT_PWM connected to PWM input(s) of backlight solution(s)
eDP / DP
DPx_TX[3:0]+/– connected to D[3:0]+/– pins on eDP/DP connector (See DP/HDMI Pin Mapping table & Signal Terminations)
DPx_AUX_CH+/– connected to Aux Lane of panel/connector (See Signal Terminations)
DPx_HPD connected to HPD pin of panel/connector
Any EMI/ESD devices used are suitable for highest frequencies supported (low capacitive load: <1pf recommended)
HDMI
DPx_TX3+/– connected to C–/C+ & pins on HDMI Connector (See Signal Terminations)
DPx_TX[2:0]+/– connected to D[0:2]+/– pins (See DP/HDMI Pin Mapping table) (See Signal Terminations)
DPx_HPD connected to HPD pin on HDMI Connector (See Signal Terminations)
HDMI_CEC connected to CEC on HDMI Connector through gating circuitry.
DPx_AUX_CH+ connected to SCL & DPx_AUX_CH– to SDA on HDMI Connector (See Signal Terminations)
HDMI 5V Supply connected to +5V on HDMI Connector.
See HDMI section for Common Mode Choke requirements if this is required (not recommended unless EMI issues seen)
See HDMI section for ESD requirements. ON-Semiconductor ESD8040 device is recommended
Video Input
Camera (CSI)
CSI[5:0]_CLK+/– connected to clock pins of camera. See CSI D-PHY Configurations table for details
CSI[5:0]_D[1:0]+/– connected to data pins of camera. See CSI D-PHY Configurations table for details
Any EMI/ESD devices used are suitable for highest frequencies supported (low capacitive load: <1pf recommended)
Control
I2C_CAM_CK/DAT connected to I2C SCL & SDA pins of imager (See Signal Terminations).
CAM[1:0]_MCLK connected to Camera reference clock inputs.
GPIO1_CAM1_PWR# / GPIO0_CAM0_PWR# connected to powerdown pins on camera(s).
GPIO4_CAM_STROBE connected to camera strobe circuit unless strobe control comes from camera module.
CAM_FLASH_EN connected to enable of flash circuit
If a module GPIO is used for flash control, CAM_FLASH_EN and/or CAMR_STROBE pins are used
GPIO3_CAM1_RST# / GPIO2_CAM0_RST# connected to reset pin on any cameras with this function.
If AutoFocus Enable is required, GPIO3_CAM1_RST# connected to AF_EN pin on camera module & GPIO2_CAM0_RST# used as
common reset line.
Audio
Codec/I2S/DMIC/DSPK
I2S0 used for Audio Codec if present in design
I2S2 used for BT if present in design
I2S[3:0]_SCLK Connect to I2S/PCM CLK pin of audio device.
I2S[3:0]_LRCK Connect to Left/Right Clock pin of audio device.
I2S[3:0]_SDATA_OUT Connect to Data Input pin of audio device.
I2S[3:0]_SDATA_IN Connect to Data Output pin of audio device.
AUD_MCLK Connect to clock pin of Audio Codec.
GPIO8_AUD_RST Connect to reset pin of Audio Codec.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618 83