Nvidia Jetson TX2 Manual page 24

Module Pin
Pin # Tegra Signal
Name
C46 PEX2_CLKREQ# PEX_L1_CLKREQ_N
D49 PEX2_RST# PEX_L1_RST_N
F43 USB_SS0_RX+ PEX_RX0P
F44 USB_SS0_RX– PEX_RX0N
C43 USB_SS0_TX+ PEX_TX0P
C44 USB_SS0_TX– PEX_TX0N
G45 SATA_RX+ PEX_RX5P
G46 SATA_RX– PEX_RX5N
D45 SATA_TX+ PEX_TX5P
D46 SATA_TX– PEX_TX5N
D47 SATA_DEV_SLP PEX_L2_CLKREQ_N
The table below show several w ays to bring out as many of the USB 3.0 or PCIe interf aces as possible to meet different design
requirements for a platform built for Jetson TX2/TX2i.
Note: Check the Jetson TX1 and Jetson TX2 Comparison and Migration Application Note which
provides the differences in USB 3.0, PCIe & SATA lane mapping between Jetson TX1 & Jetson
TX2/TX2i and provides a table of configurations supported by all three modules.
Table 15. USB 3.0, PCIe & SATA Lane Mapping Configurations
Module Pin Names
Tegra Lanes
Avail. Outputs from the
module
Configs USB 3.0 PCIe
0 1x1 + 1x4
1
1 1x4
2 (CB
Default)
2 3x1
3
4 3 2x1
5 1 2x1 + 1x2
2 1x1 + 1x2
6
Default Usage on CB (carrier board)
Note:
PCIe interface #2 can be brought to the PEX1 pins, or USB 3.0 port #1 to the USB_SS0 pins on Jetson TX2/TX2i depending
1.
on the setting of a multiplexor on the module. The selection is controlled by QSPI_IO2 configured as a GPIO.
Jetson TX2/TX2i has been designed to enable use cases listed in the table above. However, released Software may not
2.
support all configurations, nor has every configura tion been validated.
o
Configuration #1 & 2 represent the supported and validated Jetson TX2/TX2i Developer Kit configurations. These
configurations are supported by the released Software, and the PCIe, USB 3.0, and SATA interfaces have been
verified on the carrier board.
The cell colors highlight the different PCIe interfaces and USB 3.0 ports. Light and Medium green are used for PCIe
3.
controllers #0 and #1. Four shades of blue are used for USB 3.0 controllers #[0:3]. SATA is highlighted in orange.
Any x4 configuration can be used as a single x2 using only lanes 0 & 1 or a single x1 using only lane 0. Any x2
4.
configuration can be used as a single x1 using only lane 0.
In order to ease routing, the order of lanes for PCIe #0 can either be as shown above, or the reverse (I.e., PCIE#0_3 on
5.
lane 4, PCIE#0_2 on lane 3, etc.).
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Usage/Description
PCIE 2 Clock Request (PCIe IF #1)
PCIe 2 Reset (PCIe IF #1)
USB SS 0 Receive+ (USB 3.0 Port #0 muxed w/PCIe #2
Lane 0)
USB SS 0 Receive– (USB 3.0 Port #0 muxed w/PCIe #2
Lane 0)
USB SS 0 Transmit+ (USB 3.0 Port #0 muxed w/PCIe #2
Lane 0)
USB SS 0 Transmit– (USB 3.0 Port #0 muxed w/PCIe #2
Lane 0)
SATA Receive+
SATA Receive–
SATA Transmit+
SATA Transmit–
SATA Device Sleep or PEX1_CLKREQ# (PCIe IF #2)
depending on Mux setting
PEX1 PEX_RFU
Lane 0 Lane 1
SATA
1 PCIe#2_0 PCIe#0_3
1 PCIe#0_3
1 PCIe#2_0 USB_SS#1
1 USB_SS#1
1 PCIe#2_0 USB_SS#1
1 USB_SS#1
Unused
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Usage on the
Carrier Board
USB 3.0 Type A
SATA Connector
PEX2 USB_SS1
Lane 3 Lane 2
PCIe#0_2 PCIe#0_1 PCIe#0_0
PCIe#0_2 PCIe#0_1 PCIe#0_0
PCIe#1_0 USB_SS#2 PCIe#0_0
PCIe#1_0 USB_SS#2 PCIe#0_0
PCIe#1_0 PCIe#0_1 PCIe#0_0
PCIe#1_0 PCIe#0_1 PCIe#0_0
X4 PCIe Connector
Direction
Bidir
Open Drain 3.3V, Pull-
up on the module
Output
Input
USB SS PHY, AC-
Coupled (off the
Input
Output
USB SS PHY, AC-
Coupled on carrier
Output
Input
Input
SATA PHY, AC-Coupled
on carrier board
Output
Output
Open Drain 3.3V, Pull-
Input
up on the module
PEX0 USB_SS0 SATA
(see note 1)
Lane 4 Lane 5
SATA
USB_SS#0 SATA
SATA
USB_SS#0 SATA
SATA
USB_SS#0 SATA
SATA
USB 3 Type A
Pin Type
module)
board
24