Usb, Pcie & Sata - Nvidia Jetson TX2 Manual

5.0 USB, PCIE & SATA
Jetson TX2/TX2i allow s multiple USB 3.0 & PCIe interfaces, and a single SATA interface to be brought out on the module. In
some cases, these interfaces are multiplexed on some of the module pins.
Table 13. USB 2.0 Pin Descriptions
Pin # Module Pin Name Tegra Signal
B40 USB0_D– USB0_DN
B39 USB0_D+ USB0_DP
A17 USB0_EN_OC# USB_VBUS_EN0
A36 USB0_OTG_ID (PMIC GPIO0)
B37 USB0_VBUS_DET UART5_CTS
A39 USB1_D– USB1_DN
A38 USB1_D+ USB1_DP
A18 USB1_EN_OC# USB_VBUS_EN1
B43 USB2_D– USB2_DN
B42 USB2_D+ USB2_DP
Table 14. USB 3.0, PCIe & SATA Pin Descriptions
Module Pin
Pin # Tegra Signal
Name
A44 PEX0_REFCLK+ PEX_CLK1P
A45 PEX0_REFCLK– PEX_CLK1N
C48 PEX0_CLKREQ# PEX_L0_CLKREQ_N
C49 PEX0_RST# PEX_L0_RST_N
H44 PEX0_RX+ PEX_RX4P
H45 PEX0_RX– PEX_RX4N
E44 PEX0_TX+ PEX_TX4P
E45 PEX0_TX– PEX_TX4N
G42 USB_SS1_RX+ PEX_RX2P
G43 USB_SS1_RX– PEX_RX2N
D42 USB_SS1_TX+ PEX_TX2P
D43 USB_SS1_TX– PEX_TX2N
F40 PEX2_RX+ PEX_RX3P
F41 PEX2_RX– PEX_RX3N
C40 PEX2_TX+ PEX_TX3P
C41 PEX2_TX– PEX_TX3N
G39 PEX_RFU_RX+ PEX_RX1P
G40 PEX_RFU_RX– PEX_RX1N
D39 PEX_RFU_TX+ PEX_TX1P
D40 PEX_RFU_TX– PEX_TX1N
D48 PEX_WAKE# PEX_WAKE_N
B45 PEX1_REFCLK+ PEX_CLK3P
B46 PEX1_REFCLK– PEX_CLK3N
C47 PEX1_CLKREQ# PEX_L2_CLKREQ_N
E50 PEX1_RST# PEX_L2_RST_N
H41 PEX1_RX+ PEX_RX0P
H42 PEX1_RX– PEX_RX0N
E41 PEX1_TX+ PEX_TX0P
E42 PEX1_TX– PEX_TX0N
A41 PEX2_REFCLK+ PEX_CLK2P
A42 PEX2_REFCLK– PEX_CLK2N
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Usage/Description
USB 2.0 Port 0 Data–
USB 2.0 Port 0 Data+
USB VBUS Enable/Overcurrent 0
USB 0 ID
USB 0 VBUS Detect
USB 2.0, Port 1 Data–
USB 2.0, Port 1 Data+
USB VBUS Enable/Overcurrent 1
USB 2.0, Port 2 Data–
USB 2.0, Port 2 Data+
Usage/Description
PCIe 0 Reference Clock+ (PCIe IF #0)
PCIe 0 Reference Clock – (PCIe IF #0)
PCIe 0 Clock Request (PCIe IF #0)
PCIe 0 Reset (PCIe IF #0)
PCIe 0 Lane 0 Receive+ (PCIe IF #0)
PCIe 0 Lane 0 Receive– (PCIe IF #0)
PCIe 0 Lane 0 Transmit+ (PCIe IF #0)
PCIe 0 Lane 0 Transmit– (PCIe IF #0)
USB SS 1 Receive+ (USB 3.0 Port #2 or PCIe IF #0 Lane 1)
USB SS 1 Receive– (USB 3.0 Port #2 or PCIe #0 Lane 1)
USB SS 1 Transmit+ (USB 3.0 Port #2 or PCIe IF #0 Lane 1)
USB SS 1 Transmit– (USB 3.0 Port #2 or PCIe #0 Lane 1)
PCIe 2 Receive+ (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0)
PCIe 2 Receive– (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0)
PCIe 2 Transmit+ (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0)
PCIe 2 Transmit– (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0)
PCIe RFU Receive+ (PCIe IF #0 Lane 3 or USB 3.0 Port #1)
PCIe RFU Receive– (PCIe IF #0 Lane 3 or USB 3.0 Port #1)
PCIe RFU Transmit+ (PCIe IF #0 Lane 3 or USB 3.0 Port #1)
PCIe RFU Transmit – (PCIe IF #0 Lane 3 or USB 3.0 Port #1)
PCIe Wake
PCIe Reference Clock 1+ (PCIe IF #2)
PCIe Reference Clock 1– (PCIe IF #2)
PCIE 1 Clock Request (mux option - PCIe IF #2)
PCIe 1 Reset (PCIe IF #2)
PCIe 1 Receive+ (PCIe #2 Lane 0 muxed w/USB 3.0 Port
#0)
PCIe 1 Receive– (PCIe #2 Lane 0 muxed w/USB 3.0 Port
#0)
PCIe 1 Transmit+ (PCIe #2 Lane 0 muxed w/USB 3.0 Port
#0)
PCIe 1 Transmit– (PCIe #2 Lane 0 muxed w/USB 3.0 Port
#0)
PCIe 2 Reference Clock+ (PCIe IF #1)
PCIe 2 Reference Clock– (PCIe IF #1)
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Usage on Carrier
Direction
Board
USB 2.0 Micro AB Bidir
Bidir
Bidir
Input
Input
USB 3.0 Type A Bidir
Bidir
Bidir
M.2 Key E Bidir
Bidir
Usage on the
Direction
Carrier Board
Output
Output
Bidir
Output
Input
Input
Output
Output
Input
Input
PCIe x4
Connector
Output
Output
Input
Input
Output
Output
Input
Input
Output
Output
PCIe x4 conn &
Input
M.2
Output
Output
M.2 Key E
Bidir
Output
Input
Input
USB 3.0 Type A
(Default) or M.2
Key E
Output
Output
Output
Unassigned
Output
Pin Type
USB PHY
Open Drain – 3.3V
Analog
USB VBUS, 5V
USB PHY
Open Drain – 3.3V
USB PHY
Pin Type
PCIe PHY
Open Drain 3.3V, Pull-
up on the module
PCIe PHY, AC-Coupled
on carrier board
Open Drain 3.3V, Pull-
up on the module
PCIe PHY
Open Drain 3.3V, Pull-
up on the module
PCIe PHY, AC-Coupled
on carrier board
PCIe PHY
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