Strapping Pins - Nvidia Jetson TX2 Manual

JTAG_GP0# I
(JTAG_TRST_N)
JTAG_GP1
12.6.2 Debug UART
Jetson TX2/TX2i provides UART0 for debug purposes. The connections are show n in Figure 44 and described in the table
below .
Table 85. Debug UART Connections
Module Pin Name Type
UART0_TXD O
UART0_RXD I
UART0_RTS# O
UART0_CTS# I
12.6.3 Boundary Scan Test Mode
To support Boundary Scan Test mode, the Tegra NVJTAG_SEL pin must be pulled high and Tegra must be held in reset
w ithout resetting the PMIC. The figure below illustrates this. Other requirements related to supporting Boundary Scan Test
mode are described in the "Tegra X2 Boundary Scan Requirements & Usage" document.
Figure 45. Boundary Scan Connections
Jetson TX2/TX2i
Tegra
JTAG_TRST_N
NVJTAG_SEL
SYS_RESET_N
eMMC
RESET*
PMIC
RST I/O

12.7 Strapping Pins

Jetson TX2/TX2i has one strap (FORCE_RECOV#) that is intended to be used on the carrier board. That strap is used to enter
Force Recovery mode. The other straps mentioned in this section are for use on the module by Nvidia only. They are included
here as their state at pow er-on must be kept at the level selected on the module.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
100kΩ to GND &
0.1uF to GND (on the module)
100kΩ to GND (on the module)
Termination
If level shifter implemented, 100kΩ to supply
on the non-the module side of the device.
4.7kΩ to GND or VDD_1V8 on the module for
RAM Code strapping
If level shifter implemented, 100kΩ to supply
on the non-the module side of the device.
JTAG_GP0
B1 3
100kΩ
JTAG_GP1
A11
100kΩ
VDD_1V8
RESET_OUT#
A46
RESET_IN#
A47
10kΩ
1.8V
JTAG General Purpose Pin #0: Connect to TRST pin of connector
JTAG General Purpose Pin #1: Used as select
Normal operation: Leave series resistor from
-
Scan test mode: Connect
-
shown).
Description
UART #0 Transmit: Connect to RX pin of serial device
UART #0 Receive: Connect to TX pin of serial device
UART #0 Request to Send: Connect to CTS pin of serial device
UART #0 Clear to Send: Connect to RTS pin of serial device
TRST on JTAG Connector
R1 - 0 Ω
VDD_1V8
Leave Resistors R1 & R2 uninstalled
for normal operation. Install both
for boundary scan test mode.
R2 - 0Ω
Devices requiring system reset
& System Reset Sources
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
NVJTAG_SEL
NVJTAG_SEL to VDD_1V8 (install 0Ω
not stuffed.
resistor as
72