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Preparing the system
Figure 30
ISDN BRI acceptance testing setup for terminals
CPU
UILC
PRI
U Interface
NT1
553-3001-218
Standard 2.00
System Memory
Superloop
MISP
MISP
Network
PRI
as
PRI
Card
MPH
BRIL
Controller
Card
SILC
PRI
PRI
Peripheral Bus
BRSC
SILC
PRI
PRI
S/T Interface
September 2004
CPU Bus
Network Bus
Network
as
PRI
Card
S/T Interface
S/T Interface
Terminating
resistor
553-7706