Figure 11
Clock reference cable connection
NTND70AA
NTND71AA - AD
IPE I/O panel
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Clock recovery
The SILC is configured in the slave-slave mode when acting as a trunk
interface. This is configured through the Maintenance Signaling Channel
(MSC). The microcontroller configures the S/T chips on the SILC as
appropriate.
The SILC can recover the network clock from the received data stream using
on-chip phase lock loops. The clock frequency that is recovered is 2.56 MHz.
The jitter and wander conform to CCITT recommendations.
All of the S/T chips on the SILC could be configured as Terminal Equipment
Slaves (TES), but only the clocks recovered from DSL0 and DSL1 are routed
ISDN Basic Rate Interface
Installing ISDN BRI hardware
CE I/O panel
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Installation and Configuration