Pll Post-Divider Control Register (Postdiv); Pll Controller Command Register (Pllcmd); Pll Post-Divider Control Register (Postdiv) Field Descriptions; Pll Controller Command Register (Pllcmd) Field Descriptions - Texas Instruments AM1802 Reference Manual

PLLC Registers

7.3.23 PLL Post-Divider Control Register (POSTDIV)

The PLL post-divider control register (POSTDIV) is shown in
31
15 14
POSTDEN
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-26. PLL Post-Divider Control Register (POSTDIV) Field Descriptions
Bit Field Value
31-16 Reserved 0
15 POSTDEN
0
1
14-5 Reserved 0
4-0 RATIO 0-1Fh

7.3.24 PLL Controller Command Register (PLLCMD)

The PLL controller command register (PLLCMD) contains the command bit for phase alignment. A write of
1 initiates the command; a write of 0 clears the bit, but has no effect. PLLCMD is shown in
and described in Table
31
15
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset
Table 7-27. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit Field Value
31-1 Reserved 0
0 GOSET
0
1
92
Phase-Locked Loop Controller (PLLC)
Figure 7-24. PLL Post-Divider Control Register (POSTDIV)
Reserved
Reserved
R-0
Description
Reserved
Post-divider enable.
Post-divider is disabled.
Post-divider is enabled.
Reserved
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL post-divide by 2).
7-27.
Figure 7-25. PLL Controller Command Register (PLLCMD)
Reserved
Reserved
R-0
Description
Reserved
GO bit for phase alignment.
Clear bit (no effect)
Phase alignment
Copyright © 2011, Texas Instruments Incorporated
Figure 7-24 and described in
R-0
5
R-0
www.ti.com
Table 7-26.
4
RATIO
R/W-1
Figure 7-25
1
GOSET
R/W0C-0
SPRUGX5A – May 2011
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