Ddr2/Mddr Memory Controller Clocking Diagram; Ddr2/Mddr Memory Controller Mclk Frequencies - Texas Instruments AM1802 Reference Manual

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Figure 6-3. DDR2/mDDR Memory Controller Clocking Diagram
PLL0_SYSCLK2/2
PLL1
Multiplier
OSCIN Register
Frequency Setting
24 18h
24 15h
24 14h
(1)
See Section 6.2 for explanation of POSTDIV divider modes.
SPRUGX5A – May 2011
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LPSC #6
PLL1_SYSCLK1
Table 6-5. DDR2/mDDR Memory Controller MCLK Frequencies
PLL1 PLL1 Post
Multiplier Divider Mode
(1)
Frequency
600 MHz Div2
528 MHz Div2
504 MHz Div2
Copyright © 2011, Texas Instruments Incorporated
On Chip
DDR2/mDDR
Memory
Controller
VCLK
DDR
MCLK
PHY
2X_CLK
PLL1 PLL1
POSTDIV PLLDIV1
Output Register
Frequency Setting
300 MHz 8000h
264 MHz 8000h
252 MHz 8000h
Peripheral Clocking
DDR_CLK
DDR_CLK
PLL1_SYSCLK1 MCLK
300 MHz 150 MHz
264 MHz 132 MHz
252 MHz 126 MHz
65
Device Clocking