Psc0 Module Control N Register (Modules 0-15) (Mdctln); Psc0 Module Control N Register (Mdctln); Psc0 Module Control N Register (Mdctln) Field Descriptions - Texas Instruments AM1802 Reference Manual

PSC Registers

8.6.18 PSC0 Module Control n Register (modules 0-15) (MDCTLn)

The PSC0 module control n register (MDCTLn) is shown in
31 30
FORCE
R/W-0
15 11
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-23. PSC0 Module Control n Register (MDCTLn) Field Descriptions
Bit Field Value
31 FORCE
0
1
30-11 Reserved 0
10 EMUIHBIE
0
1
9 EMURSTIE
0
1
8 LRST
0
1
7-3 Reserved 0
2-0 NEXT 0-3h
0
1h
2h
3h
128
Power and Sleep Controller (PSC)
Figure 8-18. PSC0 Module Control n Register (MDCTLn)
10 9
EMUIHBIE EMURSTIE
R/W-0 R/W-0
Description
Force enable. This bit forces the module state programmed in the NEXT bit in the module control 14
register (MDCTL14), ignoring and bypassing all the clock stop request handshakes managed by the
PSC to change the state of the clocks to the module.
Note: It is not recommended to use the FORCE bit to disable the module clock, unless specified.
Force is disabled.
Force is enabled.
Reserved
Interrupt enable for emulation alters module state. This bit applies to ARM module (module 14).
Disable interrupt.
Enable interrupt.
Interrupt enable for emulation alters reset. This bit applies to ARM module (module 14).
Disable interrupt.
Enable interrupt.
Module local reset control. This bit applies to ARM module (module 14).
Assert local reset
De-assert local reset
Reserved
Module next state.
SwRstDisable state
SyncReset state
Disable state
Enable state
Copyright © 2011, Texas Instruments Incorporated
Figure 8-18 and described in
Reserved
R-0
8 7
LRST Reserved
R/W-0 R-0
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Table 8-23.
16
3 2 0
NEXT
R/W-0
SPRUGX5A – May 2011
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