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Clock Management
9.5
Clock Management
9.5.1 Module Clock ON/OFF
The module clock on/off feature allows software to disable clocks to module individually, in order to reduce
the module's dynamic/switching power consumption down to zero. This device is designed in full static
CMOS; thus, when a module clock stops, the module's state is preserved and retained. When the clock is
restarted, the module resumes operating from the stopping point.
NOTE: Stopping clocks to a module only affects dynamic power consumption, it does not affect
static power consumption of the module or the device.
The power and sleep controller (PSC) module controls module clock gating. If a module's clock(s) is
stopped while being accessed, the access may not occur, and it can potentially result in unexpected
behavior. The PSC provides some protection against such erroneous conditions by monitoring the internal
bus activity to ensure there are no accesses to the module from the internal bus, before allowing module's
internal clock to be gated. However, it is still recommended that software must ensure that all of the
transactions to the module are finished prior to disabling the clocks.
The procedure to turn module clocks on/off using the PSC is described in
NOTE: To preserve the state of the module, the module state in the PSC must be set to Disable. In
this state, the module reset is not asserted and only the module clock is turned off.
Additionally some peripherals implement additional power saving features by automatically shutting of
clock to components within the module, when the logic is not active. This is transparent to you, but
reduces overall dynamic power consumption when modules are not active.
9.5.2 Module Clock Frequency Scaling
Module clock frequency is scalable by programming the PLL multiply and divide parameters. Additionally,
some modules might also have internal clock dividers. Reducing the clock frequency reduces the
dynamic/switching power consumption, which scales linearly with frequency.
Chapter 6
details the clocking structure of the device.
PLL1 frequency and the frequency constraints.
9.5.3 PLL Bypass and Power Down
You can bypass each PLL in this device. Bypassing the PLL sends a bypass clock instead of the PLL
VCO output (PLLOUT) to the system clocks of the PLLC. For PLLC0, the bypass clock is selected from
either the PLL reference clock (OSCIN) or PLL1_SYSCLK3. For PLLC1, the bypass clock is always
OSCIN. The OSCIN frequency is typically, at most, up to 50 MHZ.
You can use the OSCIN bypass mode to reduce the core and module clock frequencies to very low
maintenance levels without using the PLL during periods of very low system activity. This can lower the
overall dynamic power consumption, which is linearly proportional to the frequency.
When the PLL controller is placed in bypass mode, the PLL retains its frequency lock. This allows you to
switch between bypass mode and PLL mode without having to wait for the PLL to relock. However,
keeping the PLL locked consumes power. You can also power-down the PLL when bypassing it to
minimize the overall power consumed by the PLL module. The advantage of bypassing the PLL without
powering it down is that you do not have to incur the PLL lock time when switching back to a normal
operating level.
Chapter 6
and
Chapter 7
134
Power Management
describe PLL bypass and PLL power down.
Copyright © 2011, Texas Instruments Incorporated
Chapter
Chapter 7
describes how to program the PLL0 and
www.ti.com
8.
SPRUGX5A – May 2011
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