Master Priority Registers (Mstpri0-Mstpri2); Master Priority 0 Register (Mstpri0); Master Priority 0 Register (Mstpri0) Field Descriptions - Texas Instruments AM1802 Reference Manual

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10.4.8 Master Priority Registers (MSTPRI0-MSTPRI2)

10.4.8.1 Master Priority 0 Register (MSTPRI0)

The master priority 0 register (MSTPRI0) is shown in
31 30 28
Rsvd Reserved
R/W-0 R/W-4h
15 14 12
Rsvd Reserved
R/W-0 R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-18. Master Priority 0 Register (MSTPRI0) Field Descriptions
Bit Field Value
31 Reserved 0
30-28 Reserved 4h
27 Reserved 0
26-24 Reserved 4h
23 Reserved 0
22-20 Reserved 4h
19 Reserved 0
18-16 Reserved 4h
15 Reserved 0
14-12 Reserved 2h
11 Reserved 0
10-8 Reserved 2h
7 Reserved 0
6-4 ARM_D 0-7h
3 Reserved 0
2-0 ARM_I 0-7h
SPRUGX5A – May 2011
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Figure 10-14. Master Priority 0 Register (MSTPRI0)
27 26 24
Rsvd Reserved
R/W-0 R/W-4h
11 10 8
Rsvd Reserved
R-0 R/W-2h
Description
Reserved. Write the default value when modifying this register.
Reserved. Write the default value when modifying this register.
Reserved. Write the default value when modifying this register.
Reserved. Write the default value when modifying this register.
Reserved. Write the default value when modifying this register.
Reserved. Write the default value when modifying this register.
Reserved. Write the default value when modifying this register.
Reserved. Write the default value when modifying this register.
Reserved. Write the default value when modifying this register.
Reserved. Write the default value when modifying this register.
Reserved. Always read as 0.
Reserved. Write the default value when modifying this register.
Reserved. Always read as 0.
ARM_D port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
ARM_I port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Copyright © 2011, Texas Instruments Incorporated
Figure 10-14 and described in
23 22 20
Rsvd Reserved
R/W-0 R/W-4h
7 6 4
Rsvd ARM_D
R-0 R/W-2h
System Configuration (SYSCFG) Module
SYSCFG Registers
Table 10-18.
19 18 16
Rsvd Reserved
R/W-0 R/W-4h
3 2 0
Rsvd ARM_I
R-0 R/W-2h
159