Receive/Transmit Timer-Control Register Register Bits Summary - Texas Instruments TMS320C3x User Manual

12.2.4 Receive/Transmit Timer-Control Register
Figure 12–16. Receive/Transmit Timer-Control Register
31 16 15 12 11
xx xx
RSTAT
R
Notes: 1) R = read, W = write
2) xx = reserved bit, read as 0
Table 12–5. Receive/Transmit Timer-Control Register Register Bits Summary
Reset
Abbreviation
Value
XGO 0
XHLD 0
XC/P 0
A 32-bit receive/transmit timer-control register contains the control bits for the
timer module. At reset, all bits are set to 0. Figure 12–16 shows the register.
Bits 5 –0 control the transmitter timer. Bits 11 – 6 control the receiver timer. The
serial port receive/transmit timer function is similar to timer module operation.
It can be considered a 16-bit-wide timer. Table 12–5 describes the register
bits, bit names, and bit functions.
10 9 8
xx
RCLKSRC
RC/P
R/W R/W
Name
Transmit timer counter
restart
Transmit counter hold
signal
Transmit clock/pulse
mode control
7 6 5
RHLD XSTAT
RGO
R/W R/W R
Function
Resets and restarts the transmit timer counter.
If XGO = 1 and the timer is not held, the counter is zeroed
and begins incrementing on the next rising edge of the timer
input clock.
The XGO bit is cleared on the same rising edge. Writing 0
to XGO has no effect on the transmit timer.
If XHLD = 0, the counter is disabled and held in its current
state.
If XHLD = 1, the internal divide-by-two counter is also held so
that the counter continues where it left off.
When XC/P = 1, the clock mode is chosen. The signaling of
the status flag and external output has a 50 percent duty
cycle.
When XC/P = 0, the status flag and external output are active
for one CLKOUT cycle during each timer period.
Serial Ports
4 3 2 1
xx XCLKSRC XHLD
XC/P
R/W R/W R/W
Peripherals
0
XGO
R/W
12-25