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Mitsubishi MELSEC Q Series Reference Manual page 343

With melsec communication protocol
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(Data name)
External device
side
(Example)
(Data name)
Programmable controller CPU side
(Example)
(Data name)
Programmable controller CPU side
(Example)
3 - 283
3 WHEN COMMUNICATING USING THE QnA COMPATIBLE 3E/3C/4C FRAMES OR 4E FRAME
(1) Communication in ASCII code
(Refer to section 3.17.1.)
H –
L
H –
L
H
L
H –
L
0
6
3
0
0
0
0
0
0
1
0
0
1
E
30
36
33
30
30
30
30
30
30
31
30
30
31
45
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H –
L
H –
L
H
W
0
0
0
1
0
0
0
0
0
8
0
57
2A
30
30
30
31
30
30
30
30
30
38
30
30
H
H
H
H
H
H
H
H
H
H
H
H
H
W100 to W107
Word device registration (second block)
H
L
H –
L
H –
L
H
0
1
0
0
0
0
0
0
0
0
0
1
0
30
31
30
30
30
30
30
30
30
30
30
31
30
30
H
H
H
H
H
H
H
H
H
H
H
H
H
CPU abnormal monitoring registration ( 1)
1 If CPU abnormal monitoring is included in the monitor conditions,
specify the following fixed values for monitor condition value items
from the device code.
• Device code
• Monitoring head device : "000000"
• No. of registered points : "0001"
• Condition agreement
transmission method
• Monitor condition
• Monitor condition value : "0001"
(Refer to section 3.3.1.)
H
L
H
L
H
L
H
L
H
L
H
L
H –
0
2
0
0
0
2
0
1
0
1
D
0
30
32
30
30
30
32
30
31
30
31
44
2A
30
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H –
L
H
L
H –
0
0
2
0
0
0
0
M
0
0
0
0
0
30
32
30
30
30
30
4D
2A
30
30
30
30
30
H
H
H
H
H
H
H
H
H
H
H
H
H
W100 0
M0 to M31
Word device registration (first block)
L
H
L
H –
L
0
0
5
0
0
0
1
30
35
30
30
30
31
H
H
H
H
H
H
H
: "01"
: "00"
: "05"
(Refer to section 3.17.1.)
L
H –
L
H
L
H
L
0
0
0
0
0
0
0
0
4
0
0
0
1
30
30
30
30
30
30
30
30
34
30
30
30
31
H
H
H
H
H
H
H
H
H
H
H
H
H
H
D0 to D3
D0=99
Word device registration (first block)
L
H –
L
H
L
H
L
H –
L
0
0
0
0
2
0
0
0
2
0
0
0
0
30
30
30
30
32
30
30
30
32
30
30
30
30
H
H
H
H
H
H
H
H
H
H
H
H
H
H
M0 OFF
H –
L
0
0
6
3
30
30
36
33
H
H
H
H
3- 283

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