Mitsubishi MELSEC Q Series Reference Manual page 183

(Data name)
External device
side
(Example)
(Data name)
Programmable controller CPU side
(Example)
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3 WHEN COMMUNICATING USING THE QnA COMPATIBLE 3E/3C/4C FRAMES OR 4E FRAME
(b) Registering monitor data for the following device memories while
communicating in binary code
• Word access
• Double word access : D1500 to D1501, Y160 to Y17F, M1111 to M1142
Monitor condition not designated
Number of points to be registered
(Refer to Section 3.3.8.)
L H L H
L - H L
01 08 00 00 04 03 00 00 00 A8 00
H H H H H H H H H H H
Devices for the number of word
access points
0801
H
Register Register
D0 T0
POINT
Designate the number of access points within the following range.
For bit devices, one word access point is 16 bits and one double word access point
is 32 bits.
For word devices, one word access point is one word and one double word access
point is two words.
(1) When accessing the Q/LCPU on the station where the C24/E71 is loaded
(local station), or the Q/LCPU on the station connected on a Q/L series
supporting network system (CC-Link IE Controller Network, CC-Link IE Field
Network, MELSECNET/H, MELSECNET/10, or Ethernet) (other station)
Number of access points: 1  (number of word access points +
When registering the file registers (ZR), use the formula, (number of access
points) x 2, for calculation.
For example, to register ZRs of 15 points, the number of access points is
calculated as 30 points.
(Note that the Basic model QCPU is excluded.)
(2) When accessing the QnACPU (other station), or the QCPU/QnACPU on the
station connected on a QnA series supporting network system
(MELSECNET/10, or Ethernet) (other station)
Number of access points: 1  (number of word access points +
(3) When accessing a programmable controller CPU (other station) except (1) and
(2)
Access is disabled.
: D0, T0, M100 to M115, X20 to X2F
(Refer to Section 3.3.1.)
- H L - H L - H
L -
(100) (1500)
00 00 C2 64 00 00 90 20 00 00 9C DC 05 00
H H H H H H H H H H H H H
Devices for the number of
double word accesses points
Register
Registers Registers
D1500
16 bits for 16 bits for
and
M100 to X20 to
D1501
M115 X2F
number of double word access points) 192
number of double word access points) 96
H
L - H L - H
(1111)
A8 60 01 00 9D 57 04 00 90
H H H H H H H H H H
Registers
Registers
16 bits for 16 bits for
M1111 to
Y160 to
M1142
Y17F
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