General Control Latch Functional Block - Fluke 9100 Series Service Manual

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PIN TYPE
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A0-A2 Input
POR- Input
SRCK Input
VDD1 Input
VDD2 Input
GND1 Input
GND2 Input
XD0-XD7 Input/Output
EQ Output
TC Output
WR- Input
RD- Input
CS- Input
VPAT Input
TEN Input
XSTP Input
GATE Input
XSTR Input
XEN Input
XCK Input
PSYN Input
VLO Input
VHI Input
CD0-CD7 Input*
TLI Input
TLO Output
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* CDn inputs have an internal resistor network to control the voltage at
which they will float (the "invalid" voltage). This voltage is
approximately 1.6 V, through an effective resistance of >50 kilohms.
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Outputs
The Clock and Enable MUX block outputs the XEN and XCK- signals to the
EXT-BUS. These two control signals are sent to each custom chip. Three
parallel inverters invert the XCK signal from U18-9, and ensure a fast
rise time into the relatively high capacitance XCK- line.

General Control Latch Functional Block

The General Control Latch Block, located on the Main PCA, varies input
thresholds, clears fault conditions, and controls the Clock and Enable
Multiplexer. Figure 2-1 shows the block's functional relationship on the
Table 2-1. Custom Chip Pin Description
FUNCTION
Address Lines
Power-On Reset
1 MHz Serial-To-Parallel
Conversion Clock
Positive Voltage Supply
Positive Voltage Supply
Logic Common
Logic Common
Microprocessor Data Bus
Equal (Data Comparison Equal) Output
Test Clock Output
Write Enable
Read Enable
Chip Select
Negative Supply for DRV Outputs
Test Mode Enable
External Stop
Frequency Gate
External Start
External Enable
External Clock
Pod Sync Clock
Logic Low Threshold Reference
Voltage for Inputs CD0-CD7
Logic High Threshold Reference
Voltage for Inputs CD0-CD7
Channel Inputs
Test Channel Comparator Input
Test Channel Comparator Output
2-11
2/Theory of Operation