Vector Address Functional Block; Vector Pattern Ram Functional Block; Vector Control Ram Functional Block - Fluke 9100 Series Service Manual

2/Theory of Operation

Vector Address Functional Block

The Vector RAM Address Registers U1 and U2 are loaded by the following
procedure:
1. The least significant byte (LSB) and the most significant byte (MSB)
of the address are loaded into U4 and U3 by performing writes to
$D0X71 and $D0X61 respectively, and then writing $D0X01 with bit 7
low and then high, toggling the LOAD-RAM- signal and parallel
loading the address.
2. If any looping is to be performed during vector driving, the LSB and
MSB of the LOOP-BACK ADDRESS are loaded into U4 and U3 by performing
writes to $D0X71 and $D0X61 respectively.
3. When vector driving is to occur, a write to $D0X01 with bit 6 set
low is performed, allowing the output of U1 and U2 to be decremented.
The outputs of U1 and U2 form the current address of the vector RAM.
Whenever a RAMCLK clocks U1 and U2, their address is decremented by
one. At the same time that U1 and U2 are being decremented, RAMCLK
latches the data of the current address into the latches of the
Vector RAM Functional Block. This process continues until either the
vector driving is complete or a LOOP command occurs. The LOOP
command generates LOOP-LD- to activate the LOAD-RAM-OUT- signal.
This signal commands U1 and U2 to reload the LOOP-BACK ADDRESS (from
which the vector driving resumes).

Vector Pattern RAM Functional Block

There are ten identical Vector Pattern RAM Functional Blocks that
provide the forty output channels on the Vector Output I/O Module. Each
RAM block consists of an 8K x 8 SRAM, a 74AC273 Octal D-Type Flip-Flop, a
resistor pack, and one 74HC126 Tri-Stateable Buffer.
The resistor pack provides isolation from the D-BUS data bus. When only
the RAM has been selected to be written to, the data on the bus passes
through the resistor pack and is input to the RAM. When vectors are
driven and all devices have been selected, the resistor pack provides
enough isolation from the bus to prevent other devices from interfering
with the output of the RAM.
When vector driving occurs, the data at the current address of the RAM
is latched in the latch by LAT-CLK. This data contains one signal bit
(high or low) and one tri-state bit (on or off) for four lines of
output. The latch also has a TRISTATE- input from P1 pin 2 that, upon a
low input, clears the the latch and resets its contents to all lows,
tri-stating all 40 outputs of the I/O module.

Vector Control RAM Functional Block

The Vector Control RAM provides user-programmed (via vector files)
control signals used for looping, handshaking, Capture clocking, and
vector drive termination.
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