Ram Select Functional Block; U5 Register Bit Description (Write @ $D0X01) - Fluke 9100 Series Service Manual

Vector output i/o module
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the LOAD-RAM-HI- and LOAD-RAM-LO- signals that control the Vector RAM
Address Functional Block. For more information on the available
addresses and the signals they affect, see Table 2-6. Table 2-8
illustrates the U5 register bits used by the Output Control Functional
Block.
U10 also provides the START-ENA signal to the SSLOGIC Functional Block.
There are two conditions by which this signal can be made active. If the
CO-START output of U5 is low, setting bit 0 to a 1 when writing to
$D0X11 sets START-ENA high. If the CO-START output of U5 is set high,
START-ENA is not set high until RECV-ARM- is low.
The RECV-ARM- signal comes from the Main PCA and is generated by U23
(74HCT138). RECV-ARM- goes low when ALLCHIP- is low, D0 is low, D1 is
high, and A1 through A3 are low (i.e., the input section is armed). This
permits the input section to be armed at the same time the output
section receives the START-ENA, so that both input and output sections
can be started simultaneously.
To clear START-ENA, the CO-START line must be set low and a WRITE @
$D0X11 must be performed with bit 0 set to 0.
Table 2-8.
___________________________________________________________________________
BIT
SIGNAL
___________________________________________________________________________
7
LOAD-RAM-
6
COUNTER-ENA-
5
HSIN-POL-
4
CO-START
3
DRV/LD-
2
MUX2*1
1
MUX1*
0
MUX0*
___________________________________________________________________________
*MUX2
*MUX1
___________________________________________________________________________
0
1
1
1
1
(other)
___________________________________________________________________________

RAM Select Functional Block

The high-speed 30 ns 8K x 8 SRAM in the module must be accessed when
loading vector files, when driving vector patterns, and when setting the

U5 Register Bit Description (Write @ $D0X01)

No Load RAM
No Counter Enable
Falling Edge
Co-Start
Drive
*MUXO
1
1
0
0
0
1
1
0
1
1
1
CLOCK
INT-OSC
PSYN
RAM-STROBE
DR CLK
DECREMENT
Ground
2-21
2/Theory of Operation
0
Load RAM
Counter Enable
Rising Edge
No Co-Start
Load

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