Bus Interface Timing Diagram - Fluke 9100 Series Service Manual

2/Theory of Operation
Figure 2-6. Bus Interface Timing Diagram
The Clock and Enable Mux block enable sources include BUFENABLE, a
signal that originates from the external ENABLE synchronization line,
and PSYN (described in the previous paragraph).
The CALCLK2 signal enters the Main PCA through the Connector Code
block. Channels 1 through 39 are tied together and to CALCLK2 when the
Calibration Module is plugged in. CALCLK2 is an input to U18-13. The
ENMUX and CLKMUX signals are generated by the Control Register (U14-15
and U14-16, respectively) and are control inputs to U18. U18 generates
outputs XEN and XCK. Table 2-2 shows which signals appear on the outputs
of the multiplexer for all four states of the control inputs.
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