Chip Counter Operation; Sslogic (Start/Stop Logic) Functional Block; Signal Polarity/Control Register - Fluke 9100 Series Service Manual

2/Theory of Operation
module output to an unchanging state. There are two methods by which the
Vector Pattern RAM and the Vector Control RAM can be selected:
o To drive vectors, the DRV/LD- signal must be set high by performing
a write to the U5 register 0 ($D0X01) with bit 3 set high. This
causes all outputs of U11 (BYTE0- through BYTE9-) and the BYTE10-
output of U10 to be low, thereby selecting all vector RAM.
o To load the Vector Pattern and Control RAM, the DRV/LD- signal must
be set low by performing a write to the U5 register ($D0X01) with
bit 3 set low. Only the RAM addressed by the chip counter U9 is
selected.

CHIP COUNTER OPERATION

The output of the chip counter is decoded by U10 and U11 to determine
which BYTEx- to set low when loading the RAM. The counter is initialized
by setting the LOAD-RAM- output of U5 low (Write @ $D0X01, bit 7 low)
and toggling RAM-PORT- (Read @ $D0X41). This causes the four-bit binary
counter (U9) to parallel-load its preset value of 5. The LOAD-RAM-
signal can then be returned high. When the output of the chip counter is
5, the BYTE0- output of the U11 PAL selects static RAM chip U100. A
write to RAM-PORT- causes the selected RAM to load the data on the bus
and advances the chip counter U9 output to 6, causing U11 output BYTE1-
to select U102. This operation is repeated until the counter reaches 15,
at which point the U10 PAL output BYTE10- selects the Control RAM U600.
Upon performing a write to RAM-PORT-, the Control RAM is loaded with the
data, and the RC0 output of U9 goes low.
The RC0 output is used as the DECREMENT- clock. The clock is routed to
the SSLOGIC block where it decrements the Vector RAM Address Register.
The RC0 output is also routed through U7 to reload the U9 chip counter
to the starting count of 5.

SSLOGIC (Start/Stop Logic) Functional Block

The SSLOGIC Functional Block consists of five groups of circuitry:
o

Signal polarity/control register.

o Drive clock selection.
o Start/stop control.
o Handshake synchronization.
o Vector drive complete logic.
SIGNAL POLARITY/CONTROL REGISTER
The output section signal polarity and control is determined by the
values stored in register U6. The values are set by performing a write
to $D0Xll with the desired value. Table 2-9 contains the register bit
assignments. Bits 4 through 7 control the active edge polarity of the
externally supplied START, STOP, ENABLE, and DR CLK signals. Bit 3
2-22