Handshake Synchronization - Fluke 9100 Series Service Manual

2/Theory of Operation
SSGATE- on U12 pin 6 provides the qualifying signal to the clock. In
order to have the clock qualified, the following conditions must be met:
o U12 pin 1 must be high. This line insures that a start has been
received, either by the FOR-START- line being low or by the STRP
signal having the programmed edge on the external START line.
o U12 pin 2 must be high. This line ensures that no external STOP
signal of the programmed edge has been received or that vector
driving is not yet complete (DONE- on U13 pin 1 clears the pin 5
output, thereby disabling SSGATE-).
o U12 pin 4 must be high. This is the ENA-RCVD line, and is either
high all the time (if ENA-ALWAYS is high) or high only when the
input on the external ENABLE line is at the programmed level.
o U12 pin 5 must be high. This is the HS-ENABLE line and is high if
vector driving is not suspended awaiting a WAIT input. If a WAIT
statement has been reached in the vector file, the HSOUT line of the
Vector Control RAM is active and sets the HS-ENABLE low, suspending
vector driving. (The following text describes handshake
synchronization in more detail.)

HANDSHAKE SYNCHRONIZATION

The handshake synchronization circuitry allows the Vector Output I/O
Module to suspend vector driving until the desired edge has been
detected on the WAIT input (P1 pin 3) of the Main PCA.
The handshake synchronization circuit consists of a 74ACT74 Dual D-Type
Flip-Flop (U8), a 74AC20 Quad Input NAND Gate (U12), and a 74ACT86
Exclusive OR Gate (U17), all on the Top PCA.
Prior to vector driving, the START-ENA line is set low. This signal is
gated by U12 and U17 and is routed to U8-10, which initializes the
HS-ENABLE line from U8-9 high. HS-ENABLE permits SSGATE- to be low upon
receipt of a start and enable with no stop. START-ENA is returned high
to enable vector driving so that U8-10 is not being held to SET-.
HSIN-POL (U5-15) is set to the proper polarity (high) when the vector
file is loaded.
When a vector is driven and is followed by a vector file WAIT statement,
the HSOUT line (U601-16) goes high. This generates a rising edge on U8
pin 11 that sets U8-9 HS-ENABLE low, which returns SSGATE- high (i.e.,
no clocks are permitted to drive vectors). U8-8 is set high as the data
input to U8-2. Upon the receipt of the proper edge on Pl pin 3 (WAIT) on
the Main PCA, HSIN is passed through U17 to become HSIN-PLUS, providing
a rising edge to U8-3, which clocks U8, setting U8-6 low. This low
signal sets the U12-8 output high. This signal is inverted by U17 and is
applied as a low to the U8-10 SET- input. When pin 10 is set, HS-ENABLE
(U8-9) returns high, which sets SSGATE- low (allowing vectors to be
clocked out). U8-8 is also set low, which removes the SET- low signal
from U8-10. The HS-ENABLE signal also goes through J4-36 on the Top PCA
to J3-36 on the Main PCA to U25-12, where the status can be observed by
bit 2 of the Vector Drive Status Nybble.
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