Custom Chip Selection - Fluke 9100 Series Service Manual

2/Theory of Operation
shows the third least significant digit of the 5-digit hex module
address broken down into binary format. The position of the set bit(s)
determines the module(s) to be addressed.
The Vector Output I/O Module bus interface timing diagram (Figure 2-6)
shows the signals contained in the bus interface block during a read and
write cycle. Each transition point (indicated by the letters A through
I) designates the following actions:
A. The address appears on the bus. R/W- goes high, signifying a read
cycle.
B. STROBE- goes low, allowing RD- and CSX- to go active. Data bus
transceiver U8 turns on, driving data from the module to the
mainframe. Addresses and R/W- are latched by U7 and are guaranteed
valid.
C. Valid read data appears on the data bus.
D. STROBE-, RD-, and CSX- return high. Read data is guaranteed valid at
this point.
E. End of the read cycle.
F. The address appears on the bus. R/W- goes low, signifying a write
cycle.
G. STROBE- goes low, allowing WR- and CSX- to go active. Data bus
transceiver U8 turns on, receiving data from the mainframe to the
module. Addresses and R/W- are guaranteed valid.
H. STROBE-, WR-, and CSX- return high. Write data is latched into the
module registers.
I. End of the write cycle.

CUSTOM CHIP SELECTION

The Bus Interface also decodes address lines A1 through A7 from the
mainframe to determine which custom chips are enabled. As the address
signals enter the Main PCA through J1, the address lines are latched by
U7 (the latch signal is STROBE-). Address lines A7 through A4 are used
as address inputs for the decoder (U6). The outputs of U6 are gated to
determine which custom chip is enabled. Any one of the five custom chips
can be addressed, or all five of the chips can be addressed
simultaneously (no other combination of the custom chips can be
addressed within a module).
For example, to select custom chip U100, the input at U7-13 (A7) from
the address bus of the mainframe must be at logic high and U7-18 (A4),
U7-17 (A5), and U7-14 (A6) must be at logic low. When STROBE- occurs, U7
latches the logic levels on these pins. On the output lines of U7,
LAT-A7 is set at logic high, and LAT-A4, LIT-A5, and LAT-A6 are logic
2-6