Input Section Theory Of Operation; Mainframe To Bus Interface Functional Block; Mainframe Addressing Of The Module - Fluke 9100 Series Service Manual

INPUT SECTION THEORY OF OPERATION

All of the input section circuitry is located on the
Main PCA unless otherwise indicated.

Mainframe to Bus Interface Functional Block

The bus interface block connects the 9100A/9105A mainframe
microprocessor bus to the Vector Output I/O Module. The module is a
memory-mapped device, with all control performed by writing to the
module memory space. The control bus enters the module on connector J1
and consists of the following lines:
o Seven address lines, A1 through A7.
o Eight data lines, D0 through D7.
o Two differential strobe lines, STROBE+ and STROBE-.
o One control line, R/W-.
The two mainframe strobe signals, STROBE+ and STROBE-, are translated by
U9 into the module STROBE- signal. STROBE- is the key signal that
qualifies all of the bus activities and is used by U7 to latch the
addresses and R/W-, and to enable the data bus buffer. The STROBE-
signal, in conjunction with the latched version of the R/W-, generates
the read strobe (RD-) and the write strobe (WR-). The STROBE- signal and
the decoder U6 provide address decoding by generating signals AD8-
through ADE- and ALLCHIP-. Signals AD8- through ADC- and ALLCHIP- are
input to AND Gates U3 and U5 to provide the custom chip selects CS0-
through CS4-. Signals ADD- and ADE- are used as register select lines.
(The mainframe STROBE- signal has already had some amount of address
decoding. STROBE- for any particular module is only active on accesses
to addresses $DXXXX, with address bit 0 = 1, and with the proper "hot
bit" identifying the module. See the heading, "Mainframe Addressing of
the Module", further on in this section for more information on hot-bit
decoding).

MAINFRAME ADDRESSING OF THE MODULE

Memory reserved for module control occupies the mainframe addresses
$D0000 through $DFFFF. Out of this 64K-byte block, four modules can be
addressed. Lower Data Strobe (LDS-) on the mainframe qualifies all
module addresses; thus address bit 0 is effectively a 1. Addresses
within this space using Upper Data Strobe (UDS-) are unused. Figure 2-3
shows a summary of module input section address decoding. Figure 2-4
provides an addressing example.
Each of the four modules is controlled via "hot-bit decoding" of the
mainframe address lines A8 through A11. This method of decoding allows
any combination of modules to be addressed simultaneously. Figure 2-5
NOTE
2-5
2/Theory of Operation