Control Register; Data Comparison Inputs; Fuse Detection; Clock And Enable Mux Truth Table - Fluke 9100 Series Service Manual

2/Theory of Operation
Table 2-2.
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CLKMUX
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0
0
1
1
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block diagram. The ICs in this block include: a 74HC273 8-Bit Latch
(U14), an LM324 Quad Op-Amp (U2), two 2N3906 PNP transistors (Ql, Q2), a
74HC08 Quad 2-Input AND Gate (U3), a 74LS30 8-Input NAND Gate (U15), two
74LS112 Dual JK Negative-Edge-Triggered Flip-Flops (U11, U12), a 74HCT32
Quad 2-Input OR Gate (U10), and a 74HCT244 Octal Buffer (U13).

CONTROL REGISTER

Data lines from the A-D-BUS to U14 produce the DCECLR- (Data Compare
Equal Clear), GENCLR- (General Clear), FUSECLR- (Fuse Clear), ENMUX
(Enable Multiplex), CLKMUX (Clock Multiplex), and THRSH (Threshold)
signals. U14 is accessed by a write to $DXXDX, where the ADD- and WR-
signals latch data into U14. The Control Register (U14) is cleared by a
PWRUP (Power Up) signal held low by C44 to ensure a proper reset.
Figure 2-7 for the Control Register bit position.
The J2 and J3 connectors provide the input to the General Control Latch
block for detection of Clip and Calibration Modules. J2-25 and J3-25 are
the input pins to a detection circuit that provides SWLDET (the
left-hand or A Switch Detect) and SWRDET (the right-hand or B Switch
Detect) signals to generate an interrupt. The mainframe reads the
interrupt register (U13) to determine the reason for an interrupt. See
Figure 2-7 for the interrupt register bit positions.

DATA COMPARISON INPUTS

All 40 lines of the module are compared to programmable data registers
and are qualified by programmable "don't care" registers. The comparison
is done inside the custom chip(s) between the data on the input lines
and the registers, eight lines per chip. The EQ outputs (pin 55 of the
custom chip) are gated together by U15, and, when they are all high
(i.e., a comparison for all five chips has been detected), an interrupt
is generated and is input to the interrupt register (U13).

FUSE DETECTION

The FUSEDET (Fuse Detect) signal is part of the Multi-Detection area of
the General Control Latch Block.

Clock and Enable Mux Truth Table

Control In
ENAMUX
0
1
0
1
Outputs
XEN
BUFENABLE BUFCLOCK
PSYN BUFCLOCK
BUFENABLE CAPTURE-
PSYN CALCLK2
A 1A slow-blow ground fuse located on
2-12
XCK
See