Capture Clock Functional Block; Drive Status Functional Block - Fluke 9100 Series Service Manual

2/Theory of Operation
step is repeated for the other byte (either the MSB or the LSB).
Finally, another write is made to $D0X21 with bit 2 set that releases
the clear on U28.
When a vector file is driven, on the vector prior to the one designated
by the ENDLOOP statement on the vector file the LOOP output (U601-5)
goes high. This signal is passed from the Top PCA (J5-24) to the Main
PCA (J4-24) and is input to a 74AC00 NAND gate (U19). If the looping is
not complete, LOOP-DONE- is high and passes the signal to the inputs of
two 74HC40103 Counters (U26 and U27), decrementing the counters. This
signal is then fed back as LOOP-LD- to J4-25 and J5-25. It passes
through U7 (Top PCA), clocking the U1 and U2 PE- (parallel load) input,
which loads the LOOP-BACK ADDRESS that is stored in U3 and U4. Each time
the vector that contains the LOOP bit is driven, this process is
repeated until U26 has counted down to zero. The TC- output enables U27
to be decremented by the next LOOP, while U26 is rolled-over, turning
off TC-. This process continues until both counters have reached their
terminal count (which occurs one pass prior to exiting the loop). When
the terminal count is reached, U27 has its LPTC signal go low, providing
a low input to U28 pin 2. Entry into the final LOOP clocks U28 to latch
the data and set LOOP-DONE- low, disabling any further LOOPs from
passing through U19. LOOP-DONE is sent to the Top PCA SSLOGIC Functional
Block for terminating vector driving if the BOTH bit of the Vector
Control RAM is set.

Capture Clock Functional Block

When a vector file is driven with the Capture clock programmed to occur,
the CAP-CLK output at U601-2 goes high for the entire vector period.
CAP-CLK is inverted by U20 and is then "ANDed" with the RAMCLK signal
and output from U20-3. The "ANDing" of the two signals provides the
clocking edge that occurs during the middle of the vector period. The
signal is then passed through the 33 ohm series resistor R10 and passes
from J5-29 to J4-29 of the Main PCA. There the signal is inverted once
more through U19 (Main PCA) before it is routed to the input of the
Clock Mux U18-12 (Main PCA).

Drive Status Functional Block

The Drive Status circuitry is located on the Main PCA. The status of the
Vector Output I/O Module is a 4-bit code returned by performing a read
at $D0X01. Table 2-10 illustrates the significance of the bits returned.
Bit 3 contains the vector drive status (0 - complete, 1 - not complete),
bit 2 contains the HS-ENABLE status (0 - drive suspended for handshake,
1 - drive not suspended for handshake), and bit 1 and bit 0 contain the
module type ID code (Vector I/O = 01). Upon the receipt of RD- on U25-7,
the status of the DONE-signal on U25-16, the HS-ENABLE signal on U25-12,
and the ID code on U25-10 and U25-11 are output on U25-17 through
U25-20. The WR-DLY- signal on U24-1 directs the data through U24 from
the TOPDATA Bus to the A-D-Bus. The address $D0X01 ensures that LATA7-
is low to enable the data. The data is then read by the mainframe
through U8.
2-28