Clock And Enable Mux Functional Block; Clock And Enable Mux Operation; Hot-Bit Decoding Examples - Fluke 9100 Series Service Manual

connected to the data bus via U8. Eleven internal registers control each
custom chip. These registers are in turn controlled by address lines A1
through A3 and the R/W- line.
The pin-out of the custom chip is shown in Table 2-1.

Clock and Enable Mux Functional Block

The Clock and Enable Mux block is located on the Main PCA and is shown
in the Input Section Functional Block Diagram, Figure 2-1. Two ICs make
up this block: the 74HCT153 Dual 4:1 Multiplexer (U18) and the 74HCT04
Hex Inverter (U4). This block selects one of three sources for the XCK-
signal, and one of two sources for the XEN signal.

CLOCK AND ENABLE MUX OPERATION

Inputs
The Clock and Enable Mux block clock sources include BUFCLOCK, CAPTURE-,
and CALCLK2. BUFCLOCK originates from the CLOCK external synchronization
line. CAPTURE- is a user-programmable clock generated on the Top PCA by
the output section during vector driving. CAPTURE is routed to the Main
PCA through J4-29 where it is inverted by U19 and sent to U18-12.
CALCLK2, which is generated during calibration, enters the Main PCA on
J2-24 and is routed to U18-13.
The POD SYNC signal, which enters the module as a differential ECL
signal, is converted by U9 into the TTL level signal PSYN. This signal
enters the EXT-BUS and is directly applied to the custom chips as a
clocking source, to U18 as an enabling signal, and to the Top PCA
through J4 pin 1 as a vector output clock source.
Figure 2-5. Hot-Bit Decoding Examples
2-9
2/Theory of Operation