Drive Clock Selection; U6 Register Bit Description (Write @ $D0X11) - Fluke 9100 Series Service Manual

determines if the vector drive clock should be always enabled or if the
external ENABLE should be used. Bit 2 determines if the vector output
should be "force" started (no external start required) or if the
external START is required. Bit 1 determines if the external STOP signal
should terminate vector driving or not. Bit 0 is unused (the address and
position of this bit are used for clearing START-ENA).

DRIVE CLOCK SELECTION

Five different clock sources are available for use by the output
section: CLKP (from DR CLK), PSYN- (Pod Sync), INT-OSC, RAM-STROBE, and
DECREMENT (used for vector RAM loading). These clocks are input to an
8-Input Multiplexer (U14). The clock selection is controlled by the
MUX2, MUX1, and MUX0 outputs of the U5 register. The clock is selected
by performing a write to $D0X01 and setting bits 2, 1, and 0 to the
desired values. Table 2-8 shows which clocks are selected by the
different bit settings. The clock source selected for vector driving or
loading is routed from U14-5 to U19 (where it is enabled by DONE- if
vector driving is not complete) and to the SSGATE Flip-Flop U16.
Table 2-9.
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BIT
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7
6
5
4
3
2
1
0
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The PSYN signal is inverted by U20 to PSYN-. This allows the vectors to
be driven on the falling edge of PSYN (so the vectors are driven and
settled by the time the rising edge of PSYN clocks the input section.
START/STOP CONTROL
The Start/Stop Control Circuit consists of two 74ACT74 D-Type Flip-Flops
(U13 and U16), a 74AC32 OR Gate (U15), a 74AC20 Quad Input NAND Gate
(U12), and a 74AC08 AND Gate (U19).
U16 determines whether the selected clock source (from U14) decrements
the Vector RAM Address Register (and latches the RAM data out if in the
drive mode) or not. If the DONE- signal is not active on U19-1, the
clock is gated through to U16-3. If the SSGATE- line is high, the clock
is disabled. If SSGATE- is low, the rising-edge of the clock causes
CK-OUT (U16-6) to go high and is presented to the vector drive
circuitry. As soon as the clock input is no longer high, the U15
CLK-PRES output goes low (since U15 pin 5 is low as well) and sets U15,
returning the CK-OUT signal low.

U6 Register Bit Description (Write @ $D0X11)

SIGNAL
CLK-POL- Falling Edge
ENA-POL Enable High
STOP-POL- Falling Edge
START-POL- Falling Edge
ENA-ALWAYS Enable Always
FOR-START- No Forcestart
STOP-ENA- No Stop Enabled
Unused
1
Rising Edge
Enabie Low
Rising Edge
Rising Edge
No Enable Always
Forcestart
Stop Enabled
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2-23
2/Theory of Operation
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