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Table 11-17. Count Leading Zeros Instruction Timings
Mnemonic
CLZ
11.2.11
Thumb Instructions
The timing of Thumb instructions are the same as their equivalent ARM* instructions. This
mapping can be found in the ARM* Architecture Reference Manual. The only exception is the
Thumb BL instruction when H = 0; the timing in this case would be the same as an ARM* data
processing instruction.
11.3
Interrupt Latency
Minimum Interrupt Latency is defined as the minimum number of cycles from the assertion of any
interrupt signal (IRQ or FIQ) to the execution of the instruction at the vector for that interrupt. An
active system responding to an interrupt will typically depend predominantly on the PXA255
processor's internal & external bus activity.
Assuming best case conditions exist when the interrupt is asserted, e.g., the system isn't waiting on
the completion of some other operation, the core will recognize an interrupt approximately 6 core
clock cycles after the application processors interrupt controller detects an interrupt.
A sometimes more useful concept to work with is the Maximum Interrupt Latency. This is typically
a complex calculation that depends on what else is going on in the system at the time the interrupt
is asserted. Some examples that can adversely affect interrupt latency are:
•
the instruction currently executing could be a 16-register LDM,
•
the processor could fault just when the interrupt arrives,
•
the processor could be waiting for data from a load, doing a page table walk, etc., and
•
high core to system (bus) clock ratios.
Maximum Interrupt Latency can be reduced by:
•
ensuring that the interrupt vector and interrupt service routine are resident in the instruction
cache. This can be accomplished by locking them down into the cache.
•
removing or reducing the occurrences of hardware page table walks. This also can be
accomplished by locking down the application's page table entries into the TLBs, along with
the page table entry for the interrupt service routine.
Intel® XScale™ Microarchitecture User's Manual
Minimum Issue Latency
1
Performance Considerations
Minimum Result Latency
1
11-9
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