Integra DTR-8.8 Service Manual page 98

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -32
U8031: S29GL128N (128 Mbit Flash Memory)
BLOCK DIAGRAM
V
CC
V
SS
V
IO
RESET#
WE#
WP#/ACC
BYTE#
CE#
OE#
TE
L 13942296513
Vcc DETECT CIRCUIT
PIN CONFIGURATION
www
.
http://www.xiaoyu163.com
RY / BY#
STATE
CONTROL
COMMAND
REGISTER
PROGRAM VOLTAGE
GENERATOR
TIMER
A0-A22
NC 1
A22 2
A15 3
A14 4
A13 5
A12 6
A11
7
A10
8
A9
9
A8 10
A19 11
A20 12
WE#
13
RESET#
14
A21
15
WP#/ACC
16
RY/BY# 17
A18 18
A17 19
A7
20
A6
21
x ao
A5 y
22
A4
23
A3
24
i
A2
25
A1
26
27
NC
28
NC
http://www.xiaoyu163.com
8
SELECTER SWITCH
ERASE VOLTAGE
GENERATOR
CHIP ENABLE
OUTPUT ENABLE
LOGIC
Y-DECODER
STB
Q Q
3 6 7 1 3
X-DECODER
u163
.
TX-NR905/NA905
2 9 9 4 2 8
DQ15-DQ0(A1)
INPUT/OUTPUT
BUFFER
DATA
STB
LATCH
Y-GATE
1 5 0 5 8 2 9 9 4
CELL MATRIX
NC
56
NC
55
A16
54
BYTE#
53
V
52
SS
DQ15/A-1
51
DQ7
50
DQ14
49
DQ6
48
DQ13
47
DQ5
46
DQ12
45
DQ4
44
V
43
CC
DQ11
42
DQ3
41
DQ10
40
DQ2
39
m
DQ9
38
37 DQ1
DQ8
36
co
DQ0
35
34 OE#
V
33
SS
CE#
32
A0
31
NC
30
29 V
IO
9 9
2 8 9 9