Integra DTR-8.8 Service Manual page 146

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -80
Q211: RTL8100CL (Ethernet Controller with Power Management)
TERMINAL DESCRIPTION(1/4)
Symbol
PMEB
(PME#)
ISOLATEB
(ISOLATE#)
LWAKE
TE
L 13942296513
Symbol
RTT3
RTSET
CTRL25
CLKRUN
NC
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Table 1. Power Management/Isolation Interface
Type Pin No
O/D 31
I 23
O 105
Table 2. Test and Other Pins
Type Pin No
TEST 123
I/O 127
Analog 8
I/O 65
- 9~11,13~16, 18, 19, 22,
24, 45, 48, 62, 72~74,
110, 112, 116, 118,
x ao
120, 125, 126
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8
Description
Power Management Event.
Open drain, active low. Used by the RTL8100C(L) to request a
change in its current power management state and/or to indicate that
a power management event has occurred.
Isolate Pin: Active low.
Isolates the RTL8100C(L) from the PCI bus. The RTL8100C(L) does
not drive its PCI outputs (excluding PME#) and does not sample its
PCI input (including RST# and PCICLK) as long as the Isolate pin is
asserted.
LAN WAKE-UP Signal.
Signals to the motherboard that it should execute the wake-up
process. The motherboard must support Wake-On-LAN (WOL).
There are 4 output choices, active high, active low, positive pulse,
and negative pulse, that may be asserted from the LWAKE pin. See
the LWACT bit in Table 19. CONFIG 1: Configuration Register 1,
page 23, for the setting of this output signal. The default output is an
active high signal.
When a PME event is received, LWAKE and PMEB assert at the
same time if LWPME (bit4, CONFIG4) is set to 0. If LWPME is set
Q Q
3 6 7 1 3
to 1, LWAKE asserts only when PMEB asserts and ISOLATEB is
low.
This pin is a 3.3V signaling output pin.
Description
Chip Test pin.
This pin must be pulled low by a resistor.
Refer to section 9 Application Information, page 61, for the correct
value.
Use this pin and an external PNP type transistor to generate +2.5V for
the RTL8100C(L).
Clock Run.
This signal is used to request starting (or speeding up) of the clock.
CLKRUN also indicates the clock status. CLKRUN is an open drain
output as well as an input. The RTL8100C(L) requests the central
resource to start, speed up, or maintain the interface clock by the
assertion of CLKRUN. For the host system, it is an S/T/S signal. The
host system (central resource) is responsible for maintaining
CLKRUN asserted, and for driving it high to the negated (deasserted)
state.
Not Connected.
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