Integra DTR-8.8 Service Manual page 118

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -52
Q8800: ADV7401 (Multi-Format SDTV/HDTV Video Decoder)
PIN CONFIGURATION
SFL/SYNC_OUT
TE
L 13942296513
TERMINAL DESCRIPTION(1/3)
Pin No.
5, 11, 17,
40, 89
49, 50, 60,
66
6, 18
12, 39, 90
63
47, 48
51
54, 56, 58,
72, 74, 76,
53, 55, 57,
www
71, 73, 75
42, 41, 28,
27, 26, 25,
.
23, 22, 10,
9, 8, 7, 94,
93, 92, 91
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1
P32
PIN 1
2
P31
3
INT
4
CS/HS
5
DGND
6
DVDDIO
7
P15
8
P14
9
P13
10
P12
DGND 11
DVDD 12
P29 13
P28 14
15
SCLK2 16
DGND 17
DVDDIO 18
SDA2 19
P11 20
P10 21
P9 22
P8 23
P27 24
P7 25
Mnemonic Type
DGND G
AGND G
DVDDIO P
DVDD P
AVDD P
PVDD P
FB I
AIN1–AIN12 I
x ao
P2–P9, P12– O
y
P19
i
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8
ADV7401
LQFP
TOP VIEW
Q Q
3 6 7 1 3
Function
Digital ground
Analog ground
Digital I/O supply voltage (3.3 V).
Digital core supply voltage (1.8 V).
Analog supply voltage (3.3 V).
PLL supply voltage (1.8 V).
FB is a fast switch overlay input that switches between CVBS
and RGB analog signals.
Analog video input channels.
u163
Video pixel output port.
.
TX-NR905/NA905
2 9 9 4 2 8
75 AIN12
74 AIN5
73 AIN11
72 AIN4
71 AIN10
70 TEST0
69 CAPC2
68 CAPC1
67 BIAS
66 AGND
65 CML
64 REFOUT
63 AVDD
62 CAPY2
61 CAPY1
60 AGND
59 TEST1
58 AIN3
57 AIN9
56 AIN2
55 AIN8
AIN1
54
53 AIN7
1 5 0 5 8 2 9 9 4
52 SOG
FB
51
m
co
9 9
2 8 9 9