Integra DTR-8.8 Service Manual page 143

QQ
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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -77
Q206: ENVY24MT (PCI Multi-channel Audio Controller)
TERMINAL DESCRIPTION(2/2)
Symbol
PSYNC
PBCLK
PSDIN[0]
PSDOUT[1:0]
PMCLK
PRST#
XOUT1
XIN1
XOUT2
XIN2
SPMCLKIN
SPMCLKOUT
TE
L 13942296513
SPSCLK
SPDIN
SPDTX
SPSYNC
GPIO[15:4]
GPIO[3] / E²PROM
GPIO[2:1]
GPIO0 / I²S#
TESTEN#
SCANEN
MTEST[3:0]
M T N C
N C
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PROFESSIONAL MULTI-TRACK AC-LINK / I
Type Description
O Sync. Sync (AC-Link Mode) or Left / Right Clock (I2S Mode) sample clock.
I/O Serial Bit Clock. Typically output for I2S mode and input for AC-Link mode
I Serial Data In. Incoming stereo stream pair
Serial Data Output. 2 separate outbound stereo stream pairs. PSDOUT[1] can be used as
O
S/PDIF OUT copy.
O Master Clock. For AC'97 codecs or I²S converters
Cold Reset. For I²S/AC-link converters
O
Clock Out 1.
A
Clock In 1. 24.576 MHz (512*48 KHz) / 49.152 MHz (256*192KHz). Runs the core blocks.
A
A Clock Out 2.
A Clock In 2. 22.5792 MHz (512*44.1 KHz)
S/PDIF (SONY / PHILIPS DIGITAL INTERFACE)
S/PDIF Master Clock Input. Or other 128x or 256x clock for slave operation
I
S/PDIF Master Clock Output. 128x
O
O S/PDIF Serial Bit Clock.
I S/PDIF Serial Data In.
S/PDIF IEC958 Line Driver Output. The voltage divider implemen ted on the board will pull down
A, PU
signaling that the digital audio transmitter is implemented via bit CCS07[6]. Capable of driving 6mA.
O S/PDIF Frame Sync.
GENERAL PURPOSE I/O
General Purpose I/O. Capable of driving 8mA.
B, PU
General Purpose I/O. E²PROM presence indicator during power-up (default). The state is reflected
B, PU
on CCS13[7] bit. Capable of driving 8mA.
General Purpose I/O. Capable of driving 8mA.
B, PU
General Purpose I/O. Sets AC-link interface for professional section during power-up (default).
B, PU
The state is reflected on CCS05[7] bit in reverse polarity. Capable of driving 8mA.
Test Mode Enable. Do not connect for normal operation.
I, PU
Scan Test Mode Enable. Must be grounded for normal operation.
I, PU
Internal Test Pins. Do not connect for normal operation.
N o C o n n c e . t
N o C o n n c e . t
POWER AND GROUND
D g i t i l a S u p p y l V l o a t
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2 9
8
²
S INTERFACE
CLOCKS
Q Q
3 6 7 1 3 1 5
TEST MODE
g . e 3.3V
co
.
TX-NR905/NA905
9 4 2 8
0 5 8 2 9 9 4 2 8
m
9 9
9 9