Integra DTR-8.8 Service Manual page 154

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -88
Q215: CDCVF2505 (Clock Driver)
BLOCK DIAGRAM
CLKIN
TE
L 13942296513
PIN CONFIGURATION
www
.
http://www.xiaoyu163.com
PLL
1
Powerdown
Edge Detect
Typical < 10 MHz
(TOP VIEW)
CLKIN
1 8
1Y1
2 7
1Y0
3 6
GND
4 5
x ao u163
y
i
http://www.xiaoyu163.com
2 9
8
25 ohm
25 ohm
25 ohm
25 ohm
25 ohm
Q Q
3 6 7 1 3 1 5
3–State
CLKOUT
1Y3
NC
1Y2
co
.
TX-NR905/NA905
9 4 2 8
8
CLKOUT
3
1Y0
2
1Y1
5
1Y2
7
1Y3
0 5 8 2 9 9 4 2 8
m
9 9
9 9