Integra DTR-8.8 Service Manual page 152

QQ
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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -86
Q213, Q214: K4M563233G (256 Mbit SDRAM)
LOGIC DIAGRAM
CLK
ADD
LCKE
L R
TE
L 13942296513
CLK
PIN CONFIGURATION
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Bank Select
A S L C B R L W E
Timing Register
CKE CS RAS
9 8 7 6 5 4
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
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8
Data Input Register
2M x 32
2M x 32
2M x 32
2M x 32
Column Decoder
Latency & Burst Length
Programming Register
L C A S
Q Q
3 6 7 1 3
CAS WE DQM
3 2 1
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FBGA Package
TX-NR905/NA905
2 9 9 4 2 8
L W C B R L D Q
1 5 0 5 8 2 9 9 4
m
co
#A1 Ball Origin Indicator
9 9
LWE
LDQM
DQi
M
2 8 9 9