Integra DTR-8.8 Service Manual page 148

QQ
3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -82
Q211: RTL8100CL (Ethernet Controller with Power Management)
TERMINAL DESCRIPTION(3/4)
Symbol
IRDYB
TRDYB
TE
PAR
L 13942296513
PERRB
SERRB
STOPB
RSTB
www
.
http://www.xiaoyu163.com
Table 3. PCI Interface(Continued)
Type Pin No
S/T/S 63
S/T/S 67
T/S 76
S/T/S 70
O/D 75
S/T/S 69
I 27
x ao u163
y
i
http://www.xiaoyu163.com
2 9
8
Description
Initiator Ready.
This indicates the initiating agent's ability to complete the current
data phase of the transaction.
As a bus master, this signal will be asserted low when the
RTL8100C(L) is ready to complete the current data phase
transaction. This signal is used in conjunction with the TRDYB
signal. Data transaction takes place at the rising edge of CLK when
both IRDYB and TRDYB are asserted low. As a target, this signal
indicates that the master has put data on the bus.
Target Ready.
This indicates the target agent's ability to complete the current phase
of the transaction.
As a bus master, this signal indicates that the target is ready for the
data during write operations and holds the data during read
operations. As a target, this signal will be asserted low when the
(slave) device is ready to complete the current data phase transaction.
This signal is used in conjunction with the IRDYB signal. Data
transaction takes place at the rising edge of CLK when both IRDYB
and TRDYB are asserted low.
Q Q
Parity.
3 6 7 1 3 1 5
This signal indicates even parity across AD31-0 and C/BE3-0
including the PAR pin. As a master, PAR is asserted during address
and write data phases. As a target, PAR is asserted during read data
phases.
Parity Error.
When the RTL8100C(L) is the bus master and a parity error is
detected, the RTL8100C(L) asserts both the SERR bit in ISR, and
Configuration Space command bit 8 (SERRB enable). Next, it
completes the current data burst transaction, then stops operation and
resets itself. After the host clears the system error, the RTL8100C(L)
continues its operation.
When the RTL8100C(L) is the bus target and a parity error is
detected, the RTL8100C(L) asserts this PERRB pin low.
System Error.
If an address parity error is detected and Configuration Space Status
register bit 15 (detected parity error) is enabled, the RTL8100C(L)
asserts both the SERRB pin low, and bit 14 of the Status register in
Configuration Space.
Stop.
Indicates the current target is requesting the master to stop the current
transaction.
Reset.
When RSTB is asserted low, the RTL8100C(L) performs an internal
system hardware reset. RSTB must be held for a minimum of 120ns.
co
.
TX-NR905/NA905
9 4 2 8
0 5 8 2 9 9 4 2 8
m
9 9
9 9