Integra DTR-8.8 Service Manual page 142

QQ
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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -76
Q206: ENVY24MT (PCI Multi-channel Audio Controller)
TERMINAL DESCRIPTION(1/2)
I - Input Signal
O - Output Signal
B - Bidirectional Signal
OD - Open Drain
A - Analog Signal
PU - Pull-up. 50 kohm nominal
Symbol
AD[31:0]
CBE#[3:0]
PCICLK
DEVSEL#
FRAME#
GNT#
IDSEL
TE
INTA#
L 13942296513
IRDY#
PAR
REQ#
RST#
STOP#
TRDY#
SDA
SCLK
TX1
RX1
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Type
Description
Multiplexed PCI Address / Data Bus.
B
B Bus Command / Byte Lane Enable. These signals are bus commands during the address phase
and byte lane enable during the data phase. These signals are output during a bus master cycle.
I PCI Bus Clock.
Device Select. The VT1720T drives this signa l active when it decodes its address as the current target
B
of the current acces.
B
PCI Cycle Frame. When asserted by the bus mster, this signal indicates the beginning of a bus
transaction.During the final data phase of a bus transaction it is deasserted.
PCI Bus Grant. When active it indicates bus master is granted to the VT1720T.
I
Initialization Device Select. This is the chip select during the PCI configuration register accesses
I
OD PCI Interrupt Request.
B
Initiator Ready.
B
Parity.
O
Bus Master Control Request.
I System Reset. All VT1720T registers and state machines are at default when this signal is asserted.
B
Target Disconnect.
B
Target Ready.
B Serial Data.
O Serial Bit Shift Clock.
MPU-401 Transmit Data.
O, PU
I, PU MPU-401 Receive Data.
x ao
y
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8
PCI BUS INTERFACE
Q Q
3 6 7 1 3
²
I C PORT
MPU-401 UART
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TX-NR905/NA905
2 9 9 4 2 8
1 5 0 5 8 2 9 9 4
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9 9
2 8 9 9