Integra DTR-8.8 Service Manual page 105

QQ
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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -39
Q3651 : ES29LV800ET-70TG (8 Mbit Flash Memory)
PIN CONFIGURATION
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
TE
L 13942296513
TERMINAL DESCRIPTION
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1
2
3
4
5
48-Pin Standard TSOP
6
7
8
9
10
11
12
ES29LV800
13
14
15
16
17
18
19
20
21
22
23
24
Pin
A0-A18 19 Addresses
DQ0-DQ14 15 Data Inputs/Outputs
DQ15 (Data Input/Output, Word Mode)
DQ15/A-1
A-1 (LSB Address Input, Byte Mode)
CE# Chip Enable
OE# Output Enable
WE# Write Enable
RESET# Hardware Reset Pin, Active Low
BYTE# Selects 8-bit or 16-bit mode
RY/BY# Ready/Busy Output
3.0 volt-only single power supply
Vcc
(see Product Selector Guide for speed options and voltage supply tolerances)
Vss Device Ground
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y
NC Pin Not Connected Internally
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2 9
8
Q Q
3 6 7 1 3 1 5
Description
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TX-NR905/NA905
9 4 2 8
48
A16
47
BYTE#
46 Vss
45 DQ15/A-1
44 DQ7
DQ14
43
DQ6
42
DQ13
41
40 DQ5
39 DQ12
38 DQ4
37 Vcc
36 DQ11
35 DQ3
34 DQ10
33 DQ2
DQ9
32
31 DQ1
30 DQ8
DQ0
29
OE#
28
27 Vss
CE#
26
25 A0
0 5 8 2 9 9 4 2 8
m
9 9
9 9