Integra DTR-8.8 Service Manual page 86

QQ
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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -20
A
Q3401: D790E001BZDH275/D710E001BZDH275 (Audio DSP)
TERMINAL DESCRIPTION(4/5)
SIGNAL NAME
UHPI_HD[0]
UHPI_HD[1]
UHPI_HD[2]
UHPI_HD[3]
UHPI_HD[4]
UHPI_HD[5]
UHPI_HD[6]
UHPI_HD[7]
UHPI_HD[8]
UHPI_HD[9]
UHPI_HD[10]
UHPI_HD[11]
UHPI_HD[12]
UHPI_HD[13]
UHPI_HD[14]
UHPI_HD[15]
UHPI_HD[16]/HHWIL
UHPI_HD[17]
TE
L 13942296513
UHPI_HD[18]
UHPI_HD[19]
UHPI_HD[20]
UHPI_HD[21]
UHPI_HD[22]
UHPI_HD[23]
UHPI_HD[24]
UHPI_HD[25]
UHPI_HD[26]
UHPI_HD[27]
UHPI_HD[28]
UHPI_HD[29]
UHPI_HD[30]
UHPI_HD[31]
UHPI_HBE[0]
UHPI_HBE[1]
UHPI_HBE[2]
UHPI_HBE[3]
UHPI_HCNTL[0]
UHPI_HCNTL[1]
www UHPI_HAS
UHPI_HRW
UHPI_HDS[1]
.
UHPI_HDS[2]
UHPI_HCS
UHPI_HRDY
http://www.xiaoyu163.com
BALL
(1)
TYPE PULL
NO.
Universal Host-Port Interface (UHPI) Data and Control
K13 IO
K14 IO
M14 IO
L13 IO
L14 IO
N13 IO
N14 IO
P14 IO
E14 IO
F14 IO
F13 IO
G14 IO
G13 IO
H14 IO
H13 IO
J13 IO
H1 IO/I
G3 IO
G4 IO
F3 IO
F4 IO
E3 IO
D3 IO
C3 IO
P2 IO
N2 IO
N3 IO
M3 IO
L3 IO
L4 IO
L2 IO
H4 IO
Universal Host-Port Interface (UHPI) Control
C6 I
C5 I
C4 I
B2 I
D9 I
C10 I
C9 I
x D8 ao I u163
y
D7 I
i
C7 I
C8 I
D6 O
http://www.xiaoyu163.com
2 9
8
(2) (3)
GPIO
IPD Y
IPD Y
IPD Y
IPD Y
IPD Y
IPD Y
IPD Y
IPD Y
UHPI Data Bus [Lower 16 Bits]
IPD Y
IPD Y
IPD Y
IPD Y
IPD Y
IPD Y
IPD Y
IPD Y
IPD Y
IPD Y
Q Q
3 6 7 1 3
IPD Y
IPD Y
IPD Y
UHPI Data Bus [Upper 16 Bits (IO)] in the following modes:
IPD Y
• Fullword Multiplexed Address and Data
IPD Y
• Fullword Non-Multiplexed
IPD Y
UHPI_HHWIL (I) on pin UHPI_HD[16]/HHWIL and GPIO on
IPD Y
other pins in the following mode:
IPD Y • Half-word Multiplexed Address and Data
In this mode, UHPI_HHWIL indicates whether the high or
IPD Y
low half-word is being addressed.
IPD Y
IPD Y
IPD Y
IPD Y
IPD Y
IPD Y UHPI Byte Enable for UHPI_HD[7:0]
IPD Y UHPI Byte Enable for UHPI_HD[15:8]
IPD Y UHPI Byte Enable for UHPI_HD[23:16]
IPD Y UHPI Byte Enable for UHPI_HD[31:24]
IPD Y
UHPI Control Inputs Select Access Mode
IPD Y
UHPI Host Address Strobe for Hosts with Multiplexed
IPD Y
Address/Data bus
IPD Y UHPI Read/not Write Input co
IPU Y
UHPI Select Signals which create the internal HSTROBE
.
active when:
IPU Y
(UHPI_HCS == '0') & (UHPI_HDS[1] != UHPI_HDS[2])
IPU Y
IPD Y UHPI Ready Output
TX-NR905/NA905
9 4 2 8
DESCRIPTION
1 5 0 5 8 2 9 9 4
m
9 9
2 8 9 9