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INTERNAL ARCHITECTURE
processes the signals to perform the current bus cycle. These signals include the address,
data, and control outputs for accessing external memory and I/O. The Bus Interface Unit
also controls the interface to external bus masters and coprocessors.
2.2 CODE PREFETCH UNIT
The Code Prefetch Unit performs the program look ahead function of the 80386. When the
Bus Interface Unit is not performing bus cycles to execute an instruction, the Code Prefetch
Unit uses the Bus Interface Unit to fetch sequentially along the instruction byte stream.
These prefetched instructions are stored in the 16-byte Code Queue to await processing by
the Instruction Decode Unit.
Code prefetches are given a lower priority than data transfers; assuming zero wait state
memory access, prefetch activity never delays execution. On the other hand, if there is no
data transfer requested, prefetching uses bus cycles that would otherwise be idle. Instruction
prefetching reduces to practically zero the time that the processor spends waiting for the
next instruction.
2.3 INSTRUCTION DECODE UNIT
The Instruction Decode Unit takes instruction stream bytes from the Prefetch Queue and
translates them into microcode. The decoded instructions are then stored in a three-deep
Instruction Queue (FIFO) to await processing by the Execution Unit. Immediate data and
opcode offsets are also taken from the Prefetch Queue.
2.4 EXECUTION UNIT
The Execution Unit executes the instructions from the Instruction Queue and therefore
communicates with all other units required to complete the instruction. The functions of its
three subunits are as follows:
• The Control Unit contains microcode and special parallel hardware that speeds multiply,
divide, and effective address calculation.
• The Data Unit contains the ALU, a file of eight 32-bit general-purpose registers, and a
64-bit barrel shifter (which performs multiple bit shifts in one clock). The Data Unit
performs data operations requested by the Control Unit.
• The Protection Test Unit checks for segmentation violations under the control of the
microcode.
To speed up the execution of memory reference instructions, the Execution Unit partially
overlaps the execution of any memory reference instruction with the previous instruction.
Because memory reference instructions are frequent, a performance gain of approximately
nine percent is achieved.
2-3
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