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TABLE OF CONTENTS
CHAPTER 1
Page
SYSTEM OVERVIEW
1.1 Microprocessor .............................................................................................
1-1
1.2 Coprocessors..................................................................................................
1-3
1.3 Integrated System Peripheral ....................
l...................................................
1-4
1.4 Cache Controller ...........................................................................................
1-5
1.5 Clock Generator ............................................................................................
1-5
1.6 8086/80286 Family Components .... ........... ................. ..... ......... ........... .........
1-5
CHAPTER
2
INTERNAL ARCHITECTURE
2.1 Bus Interface Unit ........ ............................. ....... ....... ........................ ...............
2-2
2.2 Code Prefetch Unit ........................................................................................
2-3
2.3 Instruction Decode Unit ......................... ......... ............ ..... ......... ...... ..... ..........
2-3
2.4 Execution Unit ...............................................................................................
2-3
2.5 Segmentation Unit .........................................................................................
2-4
2.6 Paging Unit ....................................................................................................
2-4
CHAPTER
3
LOCAL BUS INTERFACE
3.1 Bus Operations ............ ........... ........... ............. ............................... ...............
3-2
3.1.1 Bus States ........................... ........... ............ ................................ ...............
3-4
3.1.2 Address Pipelining .. ............... ............................................... ....... ...............
3-5
3.1.3 32-Bit Data Bus Transfers and Operand Alignment .... ...... ...... .......... .........
3-5
3.1.4 Read Cycle .. ............... ............... .............. ...... ........... .................. ................
3-10
3.1.5 Write Cycle .................. ................. ................. ............................. ..... ...........
3-13
3.1.6 Pipelined Address Cycle ......... .............. ......... ............... .............. ..... ...........
3-14
3.1.7 Interrupt Acknowledge Cycle .................. ...... ............ ................. ..... ...........
3-17
3.1.8 Halt/Shutdown Cycle ........ ................ ...... .................. ................... ..............
3-18
3.1.9 BS16 Cycle ................................................................................................
3-19
3.1.10 16-Bit Byte Enables and Operand Alignment ........ ........ .................. .........
3·20
3.2 Bus Timing .............. .......... ................ .................. ........................... ...............
3-22
3.2.1 Read Cycle Timing .....................................................................................
3-24
3.2.2 Write Cycle Timing .....................................................................................
3-24
3.2.3 READY# Signal Timing ..............................................................................
3-25
3.3 Clock Generation ....... ............ ..... ............. ....................................... ...............
3-26
3.3.1 82384 Clock Generator .............. ........ ........... ............... ............... ...............
3-26
3.3.2 Clock Timing . ....... ................... ........ ..... ....... ................................ ..... ..........
3-26
3.3.3 Crystal Oscillator Clock Generator .. ......................... ....... ...... ...... ....... ........
3-27
3.4 Interrupts .......... .......... .............. .......... ........ ........................ ............ ....... ........
3-29
3.4.1 Non-Maskable Interrupt (NMI) ............... ......................... ...... ...... ................
3-30
3.4.2 Maskable Interrupt (INTR) ..........................................................................
3-31
3.4.3 Interrupt Latency ........................................................................................
3-31
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