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TABLE OF CONTENTS
Page
6.2.6 EPROM Interface .......................................................................................
6-9
6.2.7 SRAMlnterface ...........................................................................................
6-11
6.2.8 16-Bit Interface ...........................................................................................
6-14
6.3 Dynamic RAM (DRAM) Interface .............................................. ...... ...............
6-15
6.3.1 Interleaved Memory ....... ................... ............................... ............... ............
6-15
6.3.2 DRAM Memory Performance ................................... ....... ........... .... ............
6-15
6.3.3 DRAM Controller ....... ............................ ................... ....... ............... ............
6-16
6.3.3.1 3-CLK DRAM Controller ....................... ........................ ............... ............
6-17
6.3.3.2 2-CLK DRAM Controller .................................................. ............ ....... .....
6-21
6.3.4 DRAM Design Variations ................................ ................................ ............
6-23
6.3.5 Refresh Cycles ...........................................................................................
6-25
6.3.5.1 Distributed Refresh .................. ............ ..................................... ..............
6-25
6.3.5.2 Burst Refresh ........... .............. ......................... ........................................
6-26
6.3.5.3 DMA Refresh using the 82380 DRAM Refresh Controller ....... ................
6-26
6.3.6 Initialization ... :.............................................................................................
6-27
6.3.7 Timing AnalysiS ..........................................................................................
6-28
CHAPTER 7
CACHE SUBSYSTEMS
7.1 Introduction to Caches ..................................................................................
7-2
7.1.1 Program Locality .......................................................................... ..............
7-2
7.1.2 Block Fetch ................................................................................. ..... ..........
7-2
7.2 Cache Organizations ....................................................................... .... ..........
7-3
7.2.1 Fully Associative Cache ..............................................................................
7-3
7.2.2 Direct Mapped Cache .................................................................................
7-4
7.2.3 Set Associative Cache ...............................................................................
7-6
7.3 Cache Updating ....................... ................................. .....................................
7-8
7.3.1 Write-Through System ...............................................................................
7-8
7.3.2 Buffered Write-Through System .................................................................
7-8
7.3.3 Write-Back System ....................................................................................
7-9
7.3.4 Cache Coherency .......................................................................................
7-10
7.4 Efficiency and Performance ........ ................... .................................. .......... ....
7-12
7.5 Cache and DMA ............................................................................................
7-12'
7.6 Cache Example ........... ............................. ........................ ......................... ....
7-13
7.6.1 Example Design .......... ................................. ............ ..................................
7-14
7.6.2 Example Cache Memory Organization .. .......... ...........................................
7-14
7.6.3 Example Cache Implementation ............ .............. ..... ..................................
7-15
CHAPTERS
I/O INTERFACING
8.1 I/O Mapping versus Memory Mapping ....................... ...................... .............
8-1
8.2 8-Bit, 16-Bit, and 32-Bit I/O Interfaces ............... ........ ...................... .............
8-1
8.2.1 Address Decoding ......................................................................................
8-1
vii
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