Advertisement
Figure
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
5-1
5-2
5-3
5-4
5-5
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
8-1
8-2
8-3
8-4
8-5
8-6
8-7
TABLE OF CONTENTS
Title
32-Bit and 16-Bit Data Addressing ........................................................ .
Connecting 82384 to 80386 .................................................................. .
Using CLK to Determine Bus Cycle Start .............................................. .
Clock Generator .................................................................................... .
ADS# Synchronizer .............................................................................. .
Error Condition Caused by Unlocked Cycles ......................................... .
LOCK# Signal during Address Pipelining ............................................. ..
Bus State Diagram with HOLD State ................................................... ..
Typical RC RESET Timing Circuit .......................................................... .
RESET, CLK, and CLK2 Timing ............................................................ .
80386 System with 80287 Coprocessor ............................................... .
80386 System with 80387 Coprocessor .............................................. ..
Pseudo-Synchronous Interface .............................................................. .
Software Routine to Recognize the 80287 ............................................ .
80387 Emulator Schematic ................................................................... .
Basic Memory Interface Block Diagram ................................................. .
PAL Equation and Implementation ....................................................... ..
PAL Naming Conventions ...................................................................... .
Bus Control Logic .................................................................................. .
Bus Control Signal Timing ..................................................................... .
150-Nanosecond EPROM Timing Diagram ............................................ .
100-Nanosecond SRAM Timing Diagram .............................................. .
3-CLK DRAM Controller Schematic ...................................................... ..
3-CLK DRAM Controller Cycles ............................................................ ..
2-CLK DRAM Controller Schematic ...................................................... ..
2-CLK DRAM Controller Cycles ............................................................. .
Refresh Request Generation ................................................................. .
Cache Memory System ......................................................................... .
Fully Associative Cache Organization .................................................... .
Direct Mapped Cache Organization ....................................................... .
Two-Way Set Associative Cache Organization ..................................... .
Stale Data Problem ................................................................................ .
Bus Watching ........................................................................................ .
Hardware Transparency ........................................................................ .
Non-Cacheable Memory ........................................................................ .
Example of Cache Memory Organization .............................................. .
32-Bit to 8-Bit Bus Conversion .............................................................. .
Linear Chip Selects ................................................................................ .
Basic I/O Interface Block Diagram ......................................................... .
Basic I/O Interface Circuit ...................................................................... .
Basic I/O Timing Diagram ...................................................................... .
8274 Interface ....................................................................................... .
Single 8259A Interface .......................................................................... .
xi
Page
3-22
3-27
3-28
3-28
3-29
3-33
3-34
3-35
3-37
3-38
5-3
5-5
5-7
5-9
5-11
6-2
6-4
6-5
6-7
6-8
6-10
6-12
6-18
6-20
6-22
6-24
6-27
7-1
7-4
7-5
7-7
7-9
7-10
7-11
7-12
7-15
8-3
8-5
8-6
8-7
8-11
_ 8-14
8-16
Advertisement
