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LOCAL BUS INTERFACE
Once NA# is sampled active, it remains active internally throughout the current bus cycle.
If
NA# and READY# are active in the same CLK cycle, the state of NA# is irrelevant,
because READY # causes the start of a new bus cycle; therefore, the new address and status
signals are always output regardless of the state of NA#.
A complete discussion of the considerations for using address pipelining can be found in the
80386 Data Sheet (Order Number 231630).
3.1.7 Interrupt Acknowledge Cycle
An unmasked interrupt causes the 80386 to suspend execution of the current program and
perform instructions from another program called a service routine. Interrupts are described
in detail in Section 3.4.
The 8259A Programmable Interrupt Controller is a system component that coordinates the
interrupts of several devices (eight interrupts for a single 8259A; up to 64 interrupts with
eight cascaded 8259As). When a device signals an interrupt request, the 8259A activates
the INTR input of the 80386.
Interrupt acknowledge cycles are special bus cycles designed to activate the 8259A INTA
input that enables the 8259A to output a service-routine vector on the data bus. The 80386
performs two back-to-back interrupt acknowledge cycles in response to an active INTR input
(as long as the interrupt flag of the 80386 is enabled).
Interrupt acknowledge cycles are similar to regular bus cycles in that the 80386 bus outputs
signals at the start of each bus cycle and an active READY # terminates each bus cycle. The
cycles are shown in Figure 3-11.
• ADS# is driven low to start each bus cycle.
• Control signals
MjIO#, DjC#,
and W
jR#
are driven low to signal to interrupt-
acknowledge bus cycles. These signals must be decoded to generate the INT A input signal
for the 8259A. The decoding logic is usually included in the bus controller logic for the
particular design. Bus controller designs are discussed in Chapters 6 and 8.
o
LOCK# is active from the beginning of the first cycle to the end of the second. HOLD
requests from other bus masters are not recognized until after the second interrupt
'acknowledge cycle.
• The address driven during the first cycle is 4; during the second cycle, the address is O.
BE3#, BE2#, and BE1# are high, BEO# is low, and,A31-A3 are low for both cycles;
A2 is high for the first cycle and low for the second.
'
• The 80386 floats D31-DO for both cycles; however, at the end of the second cycle, the
service routine vector at the 8259A outputs is read by the 80386 on pins D7-DO.
• READY # must go low to terminate each cycle. '
System logic must delay READY # to extend the cycle to the minimum pulse-width require-
ment of the 8259A Programmable Interrupt Controller. In addition, the 80386 inserts at
least 160 nanoseconds of bus idle time (four Ti states) between the two cycles to match the
recovery time of the 8259A.
3-17
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