Advertisement
TABLE OF CONTENTS
Figure
Title
Page
A-3
PAL-1 Equations .....................................................................................
A-14
A-4
PAL-2 Equations .....................................................................................
A-15
B-1
80387 Emulator PAL Equations .............................................................
B-1
C-1
PAL Sampling Edges ..............................................................................
C-1
C-2
3-CLK DRAM State PAL Equations ........................................................
C-3
C-3
2-CLK DRAM State PAL Equations ........................................................
C-8
C-4
3-CLK DRAM Control PAL Equations ....................................................
C-15
C-5
2-CLK DRAM Control PAL Equations ....................................................
C-17
C-6
Refresh Interval Counter PAL Equations .............................. ........ ..........
C-20
C-7
Refresh Address Counter PAL Equations ..............................................
C-23
C-8
DRAM Circuit Timing Diagram ............................. ,..................................
C-26
Tables
Table
Title
Page
1-1
80386 System Components ...................................................................
1-1
3-1
Summary of 80386 Signal Pins ..............................................................
3-3
3-2
Bus Cycle Definitions ..............................................................................
3-4
3-3
Possible Data Transfers on 32-Bit Bus ...................................................
3-10
3-4
Misaligned Data Transfers on 32-Bit Bus ...............................................
3-13
3-5
Generation of BHE#, BLE#, and A1 from Byte Enables .......................
3-23
3-6
Byte Enables during BS16 Cycles ...... ............................... ................. ....
3-23
3-7
Output Pin States during RESET ...................................... .......... ...........
3-39
4-1
80386 Performance with Wait States and Pipelining ..............................
4-1
4-2
Performance versus Wait States and Operating Frequency ...................
4-3
6-1
Bus Cycles Generated by Bus Controller ...............................................
6-6
6-2
DRAM Memory Performance ..................................................................
6-16
6-3
Designs for Six DRAM Types .................................................................
6-28
7-1
Cache Hit Rates .....................................................................................
7-13
8-1
Data Lines for 8-Bit I/O Addresses .........................................................
8-2
8-2
Timings for Peripherals using Basic I/O Interface ...................................
8-13
8-3
AO, A1, and BHE# Truth Table ..............................................................
8-20
9-1
MUL TIBUS® I Timing Parameters ..........................................................
9-10
C-1
DRAM State PAL Pin Description ............................. ,.............................
C-2
C-2
DRAM Control PAL Pin Description ............ ............................................
C-14
C-3
Refresh Interval Counter PAL Pin Description ........................................
C-19
C-4
Refresh Address Counter PAL Pin Description .......................................
C-22
C-5
DRAM Circuit Timing Parameters ...........................................................
C-27
xiii
Advertisement
