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LOCAL BUS INTERFACE
The minimum amount of time from the output of valid write data by the access device to
the end of the write cycle is the least amount of time external logic has to read the data.
This setup time is
Three CLK2 cycles
93.75 nanoseconds
- D31-DO output delay (maximum)
- 50
nanoseconds
43.75 nanoseconds
(With N wait states)
(+ N*62.5 nanoseconds)
Data outputs are valid beyond the end of the bus cycle. This data hold time is at least
One CLK2 cycle
31.25 nanoseconds
+
D31-DO hold time (minimum)
+
1
nanoseconds
32.25 nanoseconds
(Wait states do not affect this parameter)
Wait states add the same amounts of data-to-end-of-cycle time as they do for read cycles.
(See Section 3.2.1.)
3.2.3 READY# Signal Timing
The amount of time from the output of valid address signals to the assertion of READY
#
to
end a bus cycle determines how quickly external logic must generate the READY
#
signal.
READY
#
must meet the 80386 setup time. In a nonpipelined address cycle, READY
#
signal
timing is as follows:
Four CLK2 cycles
- A31-A2 output delay (maximum)
- READY
#
setup (minimum)
(With address pipelining)
(With N wait states)
125 nanoseconds
- 38 nanoseconds
- 20 nanoseconds
67 nanoseconds
(+
62.5 nanoseconds)
(+ N*62.5 nanoseconds)
Again, pipelining and wait states increase this amount of time.
Because the efficiency of a cache depends upon quick turnaround of cache hits (i.e., when
requested data is found in the cache) the timing of the READY
#
signal is critical; therefore,
READY
#
is typically generated combination ally from the cache hit comparator. If the
READY
#
signal is returned too slowly, the speed advantage of the cache is lost.
3-25
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