Table 2.8: Counter/Timer Control Register Bit Map
20FH
R/W Counter1 Setting Register
CTR0F/CTR1F: (Counter 0/1) interrupt flag bit
CTR0Gate/CTR1Gate: (Counter 0/1) gate control bit
CTR0Out /CTR1Out: (Counter 0/1) output status bit
CTR0CLKSet /CTR1CLKSet: (Counter 0/1) clock source control bit
CTR0GateSet/CTR1GateSet: (Counter 0/1) gate source control bit
CTR0OutSet/CTR1OutSet: (Counter 0 /1) output destination control bit
CTR0IntSet/CTR1IntSet: (Counter 0/1) interrupt control bit
S0/S1: (Counter 0/1) internal clock control bit
CTR32Set: Cascaded 32-bit counter control bit
CTR32
S1
S0
Set
CTR1
CTR1
IntSet
OutSet
25
CTR1
CTR1
GateSet
CLKSet
Chapter 2