QUANTA STRATOS S210 Series S210-X2A2J Technical Manual page 17

Acronyms
T
ERM
A/D Analog to Digital
ACPI Advanced Configuration and Power Interface
ASF Alerting Standard Forum
Active-high (positive true) signals are asserted when in
the high electrical state (near power potential). Active-
Asserted
low (negative true) signals are asserted when in the
low electrical state (near ground potential).
BIOS Basic Input/Output System
BIST Built-In Self Test
At the heart of the IPMI architecture is a microcontroller
BMC
called the Baseboard management controller (BMC)
Circuitry connecting one computer bus to another,
Bridge
allowing an agent on one to access the other
BSP Bootstrap processor
Byte 8-bit quantity
CLI Command Line Interface
In terms of this specification, this describes the PC-AT
CMOS compatible region of battery-backed 128 bytes of mem-
ory, which normally resides on the baseboard
CPU Central Processing Unit
D
EFINITION
T
ERM
A signal is deasserted when in the inactive state.
Active-low signal names have "_L" appended to the
end of the signal mnemonic. Active-high signal names
Deasserted have no "_L" suffix. To reduce confusion when referring
to active-high and active-low signals, the terms one/
zero, high/low, and true/false are not used when
describing signal states.
DTC Data Transfer Controller
Electrically Erasable Programmable Read-Only Mem-
EEPROM
ory
EMP Emergency Management Port
FRU Field Replaceable Unit
GB 1024 MB.
GPIO General Purpose Input/Out
HSC Hot-Swap Controller
Hz Hertz (1 cycle/second)
2
Inter-Integrated Circuit bus
I C
IANA Internet Assigned Numbers Authority
IBF Input buffer
ICH I/O Controller Hub
ICMB Intelligent Chassis Management Bus
IERR Internal Error
IP Internet Protocol
IPMB Intelligent Platform Management Bus
XVII
A
CRONYMS
D
EFINITION